Examine the difficulty of adding a proposed ss rs1, rs2, immed (Store Sum) instruction to RISC-V. Interpretation: Mem[Reg[rs 1]] = Reg[rs2] + immediate a. Which new functional blocks (if any) do we need for this instruction? b. Which existing functional blocks (if any) require modification? C. What new signals do we need (if any) from the control unit to support this instruction? d. Modify Figure bellow to demonstrate an implementation of this new instruction. * The figure for Part D is shown in the other attached photo.
Examine the difficulty of adding a proposed ss rs1, rs2, immed (Store Sum) instruction to RISC-V. Interpretation: Mem[Reg[rs 1]] = Reg[rs2] + immediate a. Which new functional blocks (if any) do we need for this instruction? b. Which existing functional blocks (if any) require modification? C. What new signals do we need (if any) from the control unit to support this instruction? d. Modify Figure bellow to demonstrate an implementation of this new instruction. * The figure for Part D is shown in the other attached photo.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Hello. Please answer the attached Computer Organization/Design question and its parts correctly. The figure for Part D is attached in the next image.
*If you answer the question and its parts correctly, I will give you a thumbs up. Thanks.
![*
PC
Address
PCSrc
Add
Instruction
memory
Figure For PART D
IFAD
Read
register 1
Read
register 2
Write
register
Write
data
Instruction
[31-0]
Instruction
[30, 14-12]
RegWrite
Instruction
[11-7]
Registers
32
Control
Read
data 1
Read
data 2
Imm
Gen
64
ID/EX
WB
M
EX
Shift
left 1
↑
AddSum
ALU
control
ALUSrc
Zero
ALU ALU
result
ALUOP
EX/MEM
WB
M
Branch
Address
Write
data
MemWrite
Data
memory
Read
data
MemRead
MEMWB
WB
MemtoReg
MUXO](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F1223c4c6-4ebb-4911-bc0d-edb37c26385f%2F7a1812e3-3c32-4ca4-8059-8d5ec891fb80%2F0o7g7b_processed.png&w=3840&q=75)
Transcribed Image Text:*
PC
Address
PCSrc
Add
Instruction
memory
Figure For PART D
IFAD
Read
register 1
Read
register 2
Write
register
Write
data
Instruction
[31-0]
Instruction
[30, 14-12]
RegWrite
Instruction
[11-7]
Registers
32
Control
Read
data 1
Read
data 2
Imm
Gen
64
ID/EX
WB
M
EX
Shift
left 1
↑
AddSum
ALU
control
ALUSrc
Zero
ALU ALU
result
ALUOP
EX/MEM
WB
M
Branch
Address
Write
data
MemWrite
Data
memory
Read
data
MemRead
MEMWB
WB
MemtoReg
MUXO
![Examine the difficulty of adding a proposed ss rs1, rs2, immed (Store Sum) instruction
to RISC-V. Interpretation:
Mem[Reg[rs 1]]= Reg[rs2] + immediate
a. Which new functional blocks (if any) do we need for this instruction?
b. Which existing functional blocks (if any) require modification?
C. What new signals do we need (if any) from the control unit to support this instruction?
d. Modify Figure bellow to demonstrate an implementation of this new instruction.
* The figure for Part D is shown in the other attached photo.
* Please solve each part correctly, and I will provide a Thumbs Up. Thank you.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F1223c4c6-4ebb-4911-bc0d-edb37c26385f%2F7a1812e3-3c32-4ca4-8059-8d5ec891fb80%2Fm5anly_processed.png&w=3840&q=75)
Transcribed Image Text:Examine the difficulty of adding a proposed ss rs1, rs2, immed (Store Sum) instruction
to RISC-V. Interpretation:
Mem[Reg[rs 1]]= Reg[rs2] + immediate
a. Which new functional blocks (if any) do we need for this instruction?
b. Which existing functional blocks (if any) require modification?
C. What new signals do we need (if any) from the control unit to support this instruction?
d. Modify Figure bellow to demonstrate an implementation of this new instruction.
* The figure for Part D is shown in the other attached photo.
* Please solve each part correctly, and I will provide a Thumbs Up. Thank you.
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