Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? 2016 6116 C116 4216 3216 7216 5216 Word within block 01 10 3216 A216 C216 8216 9216 8216 3216 7216 C216 2716 6116 1. What is the size of the main memory for cache system B? 4116 11 2016 6116 D116 5116 2116 D216 A216 4216 8216 6116 1216 5216 A216 5216 B216 B216 D216 C116 2116 7216 C216 D216 8216 4116 A216 5216 9216 5216 B216 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read?

Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? 2016 6116 C116 4216 3216 7216 5216 Word within block 01 10 3216 A216 C216 8216 9216 8216 3216 7216 C216 2716 6116 1. What is the size of the main memory for cache system B? 4116 11 2016 6116 D116 5116 2116 D216 A216 4216 8216 6116 1216 5216 A216 5216 B216 B216 D216 C116 2116 7216 C216 D216 8216 4116 A216 5216 9216 5216 B216 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

See similar textbooks

Similar questions

Suppose a computer using direct-mapped cache has 232 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, block, and offset fields?
A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.
Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we…
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes in each block. The phy 32 bits, and the smallest addressable unit is 1 byte. (i) To what block frames of the cache can the address 000010AFH be assigned? (ii) If the addresses 000010AFH and FFFF7AXYH can be simultaneously assigned to the same Cache set, what values digits X and Y have?
Suppose a computer using direct mapped cache has 232232 words of main memory and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? To which cache block will the memory reference 000063FA16 map?
A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a. What is the cache block size (in words)? b. How many entries does the cache have? Offset 4-0 c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. We assume that each word has 4 bytes. How many entries does the cache have?
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields?
Suppose a computer using direct-mapped cache has 232 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes.Q.) What is the format of a memory address as seen by cache; that is, what are the sizes of the tag, block, and offset fields?