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Nt1310 Unit 3 Assignment 3 Counters

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We all use counters every day. Whether it be in our watches, or even something like our washing machines, digital counters are found in nearly anything that involves timing (Electronics Hub, 2015).
Counters have come a very long way over the years, increasing in both efficiency and complexity. One example of an early counter is the counter developed by Paul Stillman in 1854. This design had a small manual crank which would turn a dial by one digit each time it was cranked. Once the first dial had turned by ten digits, it would then turn the next dial by one digit (in a gradual motion). In 1920, the Veeder Manufacturing Company made a counter that replaced this manual crank, which would only allow for turning the dials one digit at a time, …show more content…

When it is set up correctly, the 555 timer in astable mode will create a square output wave with nearly perfect timing. At the start, the output of the 555 timer will be HIGH, because the output is inverted. Voltage will flow in through the C1 capacitor, gradually charging it up. At this stage, the lower capacitor (the trigger capacitor) is outputting a HIGH voltage level because the input voltage is less than ⅓ VCC, and because the input voltage is going through the negative terminal, or in other words, the voltage at the positive terminal is greater, so the output is HIGH. Once the input voltage reaches ⅓ VCC, the comparator outputs a LOW signal, because the voltage on the positive terminal is no longer greater. At this point in time however, the output of the flip flop does not change. Once the voltage input surpasses ⅔ VCC, the threshold comparator will have a HIGH output as the positive terminal is greater than the negative terminal input. This will cause the flip-flop to change state, causing the 555 timer output to change state. However as the flip-flop is also connected to the base of the NPN transistor, as the flip-flop’s complement output changes to HIGH, the capacitor begins to discharge through the transistor (How to Mechatronics, …show more content…

As these flip-flops have a positive edge trigger for the clock input, this means every time the clock input goes from LOW to HIGH, it triggers the flip-flop, updating the Q output to whatever the D input is, assuming the SET and RESET inputs of the flip-flop are both inactive, which they are in this circuit (Digital Electronics, 2014). At the start, the D input will be HIGH, because D is connected to the inverted Q output (PyroElectro, 2013). However, the 555 timer has a HIGH output at the start, but due to the fact the flip-flop triggers when the clock input goes from LOW to HIGH, the counter still starts off counting from 0, because it takes one count for the clock to go back to LOW then to HIGH again. As the clock counts, every second count of the previous flip flop will cause the next flip-flop to change state. Thinking back to simple binary theory, this makes sense. As a digit in binary is double the previous one, every second time the previous digit changes state, the next digit should change state once. As this is a four bit counter, once the fourth digit changes state from HIGH to LOW, the counter resets, and counts from zero

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