Running Head: MULTICORE PROCESSORS
Case Study 3: Managing Contention for Shared Resources on Multicore Processors
Strayer University
Instructor: Dr. Kegan Samuel
CIS 512 Advanced Computer Architecture
November 30, 2013
Abstract
This “Case Study” cover information on computer systems with multicore processors which can increase performance by running applications of various types (models) and methods. This paper focuses on applications using distributed architecture, cache contention, prefetching hardware and more. Current and future contentions are discussed. Managing contention for shared resources on multicore processors are discussed in this assignment. Explanations given for causes of contention. Discussion of the
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This is the reason why the older memory-reuse model that was designed to model cache contention only, was not effective in our environment This model was evaluated by the authors on a simulator that d. id not model contention for resources other than shared cache and it turns out that when applied to a real system that other contentions are present the model did not prove effective. On the other hand, cache miss rate turned out to be an excellent predictor for contention for the memory controller, prefetching hardware, and front-side bus, with each application in the author’s model was co-scheduled with “Milc” application to generate contention. An application that issue many cache-misses will occupy the memory controller and the front-side bus so it not only hurt other applications that use that hardware, but, end up suffering itself if this hardware is usurped by others. The investigation by the authors of contention-aware scheduling algorithms delivered a lesson to them that high-miss-rate applications must be kept apart. This means that they should not be scheduled in the same memory domain. Some restrictions have already suggested this approach, it is not well understood why using the miss rate as a proxy for contention ought to be effective, especially the fact that it contradicts the theory behind the popular
Operating Systems are complex pieces of software that are designed for powerful hardware, easily capable of running many programs at once, the prioritize hardware task requests known as ‘system calls’ and allocate them memory space or processing time as needed.
When a request is made of the system the CPU wants instructions for executing that request. The CPU works faster than system RAM, to cut down on interruptions, L1 cache has bits of data that it anticipates will be needed. L1 cache is very
Applications member with embedded caches become a part of the distributed system as peer-to-peer members. Each cache member directly communicates with other cache member.
In spite of the fact that multiprocessors have numerous favorable position it additionally have some detriment like complex in structure when contrasted with uni-processor framework.
Cache is a volatile form of storage meaning when the computer is turned off, then the data is lost. Cache cost a lot of money to make meaning it has got a higher cost per byte than ram or flash storage. The reason cache is used for storing frequently instructions near or on the CPU is because it's faster than ram and has less latency, but has a higher capacity than registers at a lower but still high cost compared to other types of storage. In conduction is that cache is a high speed form of temporary storage, which acts as a buffer between the ram and the CPU, which stores frequently used instructions which removes the speed decrease from using the system buses and has low latency and cost less than registers and has a higher
Since the invention of the first computer, engineers have been conceptualizing and implementing ways to optimize system performance. The last 25 years have seen a rapid evolution of many of these concepts, particularly cache memory, virtual memory, pipelining, and reduced set instruction computing (RISC). Individual each one of these concepts has helped to increase speed and efficiency thus enhancing overall system performance. Most systems today make use of many, if not all of these concepts. Arguments can be made to support the importance of any one of these concepts over one
-In single-processor frameworks, the memory should be redesigned when a processor issues upgrades to reserved qualities. These upgrades can be performed instantly or in a languid way. -In a multiprocessor framework, distinctive processors may be reserving the same memory area in its nearby stores. At the point when redesigns are made, the other reserved areas should be discredited or overhauled.
Memory management exists in programs and applications, hardware, and in the Operating System (OS). In the Operating System, the OS goes to the hard drive, finding the piece of file or specific memory blocks, and then copies it into the RAM. The CPU is then able to access it. The OS must find a location in the RAM where it is not being used by anything else when it copies it from the hard drive.
As technology advances, the processes that we use to manage that technology become more demanding, creating the need for new software and efficient processors. “The central processing unit or (CPU) is the heart of your computer and is used to run the operating system as well as all the programs.” (Chris Hoffman, CPU Basics: multiple CPU’s, cores and hyper threading explained.) With so much power in a single chip, we have created a powerful piece of technology that can be placed virtually anywhere.
Question 4 (d): The special case of the problem when each resource is requested by at most 2 processes.
In single-processor frameworks, the memory should be redesigned when a processor issues upgrades to reserved qualities. These upgrades can be performed instantly or in a languid way. In a multiprocessor framework, distinctive processors may be reserving the same memory area in its nearby stores. At the point when redesigns are made, the other reserved areas should be discredited or overhauled. In disseminated frameworks, consistency of stored memory qualities is not an issue. Then again, consistency issues may emerge when a customer reserves document information.
More cache means better performance, so modern processors are always looking for new and innovative ways to add more cache to a single die. Furthermore, cache is such an important feature that due to the expense of making it, most caches are divided into 3 levels of varying speeds and sizes. The highest capacity, but slowest in performance is the L3 cache, originally on the motherboard itself, it is now integrated into the processor and generally shared between all cores (Labsim). The next level is the L2 cache, faster than L3, but smaller in size. The L2 cache is located on the processor and usually has multiple of this cache for either private, per core cache, or only shared between a select few cores. The final and fastest of the caches is the L1 cache, but smallest in size of all the others. L1 is located on the processor and private to every core for quick access of small amounts of vital information
Attending of the reason an allocator can not utilize a few sections of the memory, three types of wasted memory, usually called fragmentation can be defined: it Internal fragmentation when the allocator limits the conceivable sizes of allocatable blocks because of design constraints or efficiency requirements; External fragmentation: The succession of designation and deallocation operations may abandon some memory areas unused since; and, wasted memory which relates to the memory oversaw by the allocator that can not be assigned to the application . Infact, the wasted memory whenever is the contrast between the live memory and the memory utilized by the allocator around
Accurate job scheduling has a great impact on overall system performance; depending upon various job specifications. Allocation of system resources on demand to different jobs by scheduler is known as job scheduling. But, scheduling
4. Performance Comparison of Dual Core Processors Using Multiprogrammed and Multithreaded Benchmarks ............................................................................................... 31 4.1 Overview ........................................................................................................... 31 4.2 Methodology ..................................................................................................... 31 Multiprogrammed Workload Measurements .................................................... 33 4.3 4.4 Multithreaded Program Behavior ..................................................................... 36 5. 6. Related Work ............................................................................................................ 39 Conclusion ................................................................................................................ 41