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Technical Terms Used in Vlsi (Semi Conductor Design)

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Hardware Design Some Important terms: 1) HDL: Hardware Description Language e.g. VHDL and Verilog This is the language in which the design is coded. The design code is in a specific format called RTL design. 2) RTL: Register Transfer Logic The way the design is coded. 2a) flip flop: One unit for 1 memory retention. 3) Test bench: This is the program that tests the design. It applies the stimulus to the design and compares the actual output with the expected output. If the actual output is same as the expected output then the test case passes i.e the functionality is correct. If the actual output is different then the expected output then there is a bug which has to be fixed by the designer of the module which is not behaving the …show more content…

The simulators by the 3 top EDA companies are: Synopsys: VCS Cadence: Incisive simulator Mentor Graphics: Modelsim and Questasim Questasim is Modelsim with additional functionality to support System Verilog. The wave form viewer can be used to view the output of the simulator as waves. This is easier to debug then just numbers that are output by the simulator. The waveform viewer becomes like a CRO probing the circuit. 12) Synthesis: The fully verified design, verified by the simulator which simulates the RTL design and the verification testbench. This design (without the testbench) is synthesized into gates. This output from the synthesis tools is a gate level netlist. The most popular synthesis tool used is Design Compiler by Synopsys. DC is the most popular synthesis tool. RTL compiler from Cadence is not that popular. 13) Timing checks: RTL design is without timing. Every transaction happens in zero time. Gate level simulation is used with timing. Static timing analysis tools can be used. 14) Gate level simulation: The output of the synthesis is tested for timings of the various gates used. The same simulator can be used and the waveforms with timing information are examined for correct functioning and timing. 15) System Verilog: A new language developed which can be used both for writing RTL (design) as well as the Full chip verification test bench. When the design is in RTL and the test bench is in

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