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1. Convert the decimal into binary. Use IEEE-32-bit floating-point format -21.875

1. Convert the decimal into binary. Use IEEE-32-bit floating-point format -21.875

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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1. Convert the decimal into binary. Use IEEE-32-bit floating-point format -21.875 2. Convert the following IEEE-32-bit floating-point number into decimal 1 1 1 1 1 1 1 0 1 0 0 3. A pipelined processor has the following internal stages: Fetch – Decode - Operand Address Calculation – Execution -- Memory Data Read – Write Result How many stages are required to clear in case of a conditional instruction evaluated TRUE. How many stages are required to clear in case of a conditional instruction evaluated FALSE. 4. Assume you have a 2-way set associative cache having 1K lines each having capacity of 4 Bytes. A Byte addressable main memory uses 32 bit physical address. The cache has a hit ratio of 90% and is initially empty. How many bytes of data are brought into the cache with physical address FAB12389H? 5. What do you understand by resource conflict in pipelining? (answer in maximum 8 words) 6. What is the main difference between Integer ALU and Floating Point ALU? (just 1 point) 7. For same sizes of RAM, Cache, block and line, which mapping technique results the lowest Tag to Data ration? (answer in maximum 2 words) 8. A computer having 16MB RAM, 16KB Cache, 16B block, 16B line uses associative mapping technique. How many Tags are checked each time when the CPU fetches any instruction? (answer in 1 word)
Transcribed Image Text:1. Convert the decimal into binary. Use IEEE-32-bit floating-point format -21.875 2. Convert the following IEEE-32-bit floating-point number into decimal 1 1 1 1 1 1 1 0 1 0 0 3. A pipelined processor has the following internal stages: Fetch – Decode - Operand Address Calculation – Execution -- Memory Data Read – Write Result How many stages are required to clear in case of a conditional instruction evaluated TRUE. How many stages are required to clear in case of a conditional instruction evaluated FALSE. 4. Assume you have a 2-way set associative cache having 1K lines each having capacity of 4 Bytes. A Byte addressable main memory uses 32 bit physical address. The cache has a hit ratio of 90% and is initially empty. How many bytes of data are brought into the cache with physical address FAB12389H? 5. What do you understand by resource conflict in pipelining? (answer in maximum 8 words) 6. What is the main difference between Integer ALU and Floating Point ALU? (just 1 point) 7. For same sizes of RAM, Cache, block and line, which mapping technique results the lowest Tag to Data ration? (answer in maximum 2 words) 8. A computer having 16MB RAM, 16KB Cache, 16B block, 16B line uses associative mapping technique. How many Tags are checked each time when the CPU fetches any instruction? (answer in 1 word)
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