1. Implement the NAND gate only. following legie. using Fa x.Y +x Z

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1. Implement the following logie using
NAND gate only.
Fa x.Y +x Z
2. Implement the folloing logic using
NOR gate only.
F= AB + BCĀ + cD + DB
a. what will be
Y1 R Yz for the tollowing PLA
3.
A tx
B
2 YL=?
-Y2%=?
Transcribed Image Text:1. Implement the following logie using NAND gate only. Fa x.Y +x Z 2. Implement the folloing logic using NOR gate only. F= AB + BCĀ + cD + DB a. what will be Y1 R Yz for the tollowing PLA 3. A tx B 2 YL=? -Y2%=?
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