Don't really know how to start solving this problem.
Using 4 bit counter we can implement a modulo 12 synchronous counter by ensuring that all the flip flops are reset to 0 as soon as 12 (i.e. binary number 1100) is reached. So if the flip flops are labelled as A,B,C and D starting from LSB to MSB then we can tie the Q outputs of flip flops C and D (both would have Q value = 1 at 12) with the Q-bar (negative of Q) outputs of A and B (both of which would have Q value = 0 at 12) and feed it to a 4 input NAND gate the output will be 0. This could be connected to the ClrN input which resets the counter to 0 (a 4 input NAND gate can be implemented using a first stage of 2 NAND feeding into an OR gate).
Sorry about that. What wasn’t helpful?