2. Assume the following register mappings: a= $t0,b=$t1, c=$+2, tmpl=$+3, tmp2=$+4 c = (a < b) && ((a+b) % 3) == 2;
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- A(n) ____________________ instruction copies data from one memory location to another.Section 3: The Control Unit For the Control Unit, you can simply use an 8-bit input switch or otherwise, which will act as the control wordinput to the data-path (we will not focus on using a control store nor selector). The control word input shouldbe based on the format shown in table 2. These values should be sent to the data-path to accomplish a giventask. In addition to the control word, you will need to implement a way of ensuring the correct register(s) areselected to either input (LOAD) or output (Open Enable) a value. Again, think about using a multiplexer orotherwise. For X0, you will not be using the value, but include it in the design.3X0 C0 C1 B0 B1 F2 F1 F0Table 2: Control Unit control word format. If the base register holds 500 and the limit register is 300, Then the program can legally access all addresses A. From 300 to 500 B. From 500 to 799 C. From 300 to 799 D. None of the above
- The table shows the delays (pico second) of the components in Figure 4.17. Read/write PC I-mem D-mem Register file Mux ALU Adder And, Shifter Sign extend Control 10 250 150 25 200 150 10 50 50 Calculate the delay of the 4 types of instructions. You need to show which components are used in each instruction. Instructions: instruction delay time sd add beq ldSpecify the register contents and flag status as the following instructions are executed. A B S Z CY MVI A, FFH RRC MOV B,A ADD B RAR DCR A HLTWhat will be the values of EDX:EAX after the following instructions execute?mov edx,100hmov eax,80000000hsub eax,90000000hsbb edx,0
- Assume that the contents of the register r16 and carry flag are 0xA5 and 1, respectively. What will be new values for r16 and C after the execution of: (a) lsl r16 (b) lsr r16 (c) rol r16 (d) ror r16 (e) asr r16 (f) swap r16Assume you have three input pins called Pin 1, Pin 2, and Pin 3. Assume you have a single 2-bit register called A. Please draw a circuit that does the following: When Pin 1 is on and Pin 2 is off and Pin 3 is off, then A stores integer 1 in binary. When Pin 1 is off and Pin 2 is on and Pin 3 is off, then A stores integer 2 in binary. When Pin 1 and Pin2 are off and Pin 3 is on, then A stores integer 3 in binary. When Pin 1, Pin 2 and Pin 3 are all off, then A stores integer 0 in binary. No other pin combinations are defined.Q2. [Structural Verilog] Design a 2-bit subtractor unit. Inputs are A and B, and output is S, 2-bits each. As a sub-module you can call the Full Adder module (E Assume this is given to you as library) which takes in 3 inputs (X, Y and Z) and produces 2 outputs (F, C). Write structural HDL
- In this instance, the operand would be the Instruction Register (IR).When a word is divided by a byte, the word must be in the a. DX register O b. BX register O c. CX register O d. AX register1. The _______represents the internal description of the design (how it works). 2. Given a universal 4 bit shift register that shifts the loaded value 0101 to the left one timethe decimal value would be______. 3. Given a universal 4 bit shift register that shifts the loaded value 0100 to the right two times, the decimal value would be______.