2.2. Draw a diagram showing how virtual addresses are translated in a paging system. (4)
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- Question 1 Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.Question 12 Suppose you have a byte-addressable virtual address memory system with 8 virtual pages of 64 bytes each, and 4 page frames. a. How many bytes are in a virtual address? b. How many bytes are in a physical address?Please explain the question below Objective: Show the influence of the cache size on the miss rate Development Configure a system with the following architectural characteristics: Processors in SMP = 1 Cache coherence protocol = MESI Scheme for bus arbitration = Random Word wide (bits) = 16 Words by block = 16 (block size = 32 bytes) Blocks in main memory = 8192 (main memory size = 256 KB) Mapping = Fully-Associative Replacement policy = LRU Configure the blocks in cache using the following configurations: 2(cache size = 0,03 KB), 4,8, 16, 32, 64, 128, 256, and 512 (cache size = 16 KB). For each of the configurations, obtain the miss rate using the trace files: Hydro, Naasa7, Cexp, Comp, and Wave. Are there conflict misses in these experiments? Why? In these cases, it may be observed that for great cache sizes, the miss rate is stabilized. Why? We can also see great differences in miss rate for a concrete increment of cache size. What do these great differences indicate?
- Operating Systems Problem Two (15 points) Paged page table A paged virtual memory has the following characteristics: The virtual address size is 32 bits. The page size is 1024 words. Each word is 1 integer. Each page table entry needs 4 integers. a) Determine the size of the page table, PT. b) The PT is too large and must be divided into a hierarchy of pages of size 1024 integers. Determine the number of levels in the hierarchy such that no PT exceeds the page size. c) Determine the size of the highest level PT in the hierarchy1) What is the difference between the status and control flags? What are the status flags for the AEH+37H operation? 2) What is the aim of segmentation as well as physical address generation? Explain with a drawing and a numerical example? 3) What is the amount of the memory in each of the following cases? • All segments are • Overall memory is 4) Given the ES=3050H, SS=1298H, and CS-ABC3H, find the physical address for a) SP=2583H, b) DI=3399H, and c) IP=18F7H.Research how the separation of policy and mechanism is achieved in a virtual memory management system and why this is important in a virtual memory management system. Write up a 200 word summary of your research that outlines the responsibilities between the MMU, the page fault handler, and the external pager function and how they all cooperate together to achieve separation of policy and mechanism.
- Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? a.How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels is needed? Draw a figure to show your page systems;Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?Consider a main memory with size 512MB with cache size 64KB and memory block is 4 bytes. Assume that the memory word is 1 byte . Answer following question How many address bits are required ti address the main memory locations ? How many blocks are there in the cache memory? Determine how to split the address (s-r, d ,w )for direct mapping? Determine how to split the address (s-d, d ,w )for set associative mapping .Assume each cache set is 4 line of cache
- 1. Consider a computer wth the following characteristics: total of 1Mbyte of mainmemory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.a) For the main memory addresses of 01234 and CABBE, give the correspondingtag, cache line address, and word values for a direct-mapped cache.b) Give any two main memory addresses (based on the format identified in (a)with different tags that map to the same cache slot for a direct-mappedcache.c) For the main memory addresses of F0010 and CABBE, give the correspondingtag and offset values for a fully-associative cache.d) For the main memory addresses of F0010 and CABBE, give the correspondingtag, cache set, and offset values for a two-way set-associative cache.Explain the relationship among physical address, segment address, and offset address. Discuss thenon-overlapping memory segmentation and overlapping memory segmentation?2. Consider a computer with the following characteristics: total of 1Mbyte of main memory; Content of each addressable location is 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. (b) Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. (c) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. (d) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache.