5. a. b. Explain Set Associative Mapping Cache Function? Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB. Find- 1. Number of bits in tag 2. Tag directory size

5. a. b. Explain Set Associative Mapping Cache Function? Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB. Find- 1. Number of bits in tag 2. Tag directory size

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Properties of different architectures

Software architectures are the blueprint of a software system. They consist of all components involved in a system, relations between various components, the environment of operation, and the principle used in designing the software. In other words, software architecture shows the organization of different software structures and helps understand their behavior.

Question

5. a.
b.
Explain Set Associative Mapping Cache Function?
Consider a 2-way set associative mapped cache of size 16 KB with block size 256
bytes. The size of main memory is 128 KB. Find-
1. Number of bits in tag
2. Tag directory size

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CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
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Problem 1 Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB. Find- Number of bits in tag Tag directory size
Consider a small 2-way set associative cache memory, consisting of 4 blocks. For choosing the block to be replaced, use LRU scheme. Consider that block address 4 and 2 are already there in cache. The number of cache misses for the following sequence of block addresses 4, 6, 8, 16, 2, 2, 4 are?
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Consider a 128-word L2 memory and a 16-word direct mapped L1 cache.a. How many bits are in the address of the L2 memory?b. How many index bits are in the L1 address?c. How many tag bits are in the L1 address?d. How many words from the L2 memory will map to the same word in L1?
Determine the cache performance of the following code:1 for (i = 0; i < 16; i++){2 for (j = 0; j < 16; j++) {3 total_x += grid[j][i].x;4 total_y += grid[j][i].y;5 }6 }A. What is the total number of reads?B. What is the total number of reads that miss in thecache?C. What is the miss rate?D. What would the miss rate be if the cache were twice asbig?
1. Suppose we have a 32KB direct-mapped data cache with 32-byteblocks.a) Show how a 32-bit memory address is divided into tag, index andoffset. Show clearly how many bits are in each field.b) How many total bits are there in this cache?