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5. The Average Memory Access Time equation (AMAT) has three components: hit time, miss rate, and miss penalty. For each of the following cache optimizations, indicate which component of the AMAT equation is improved. a. Using a second-level cache b. Using a direct-mapped cache C. Using a 4-way set-associative cache

5. The Average Memory Access Time equation (AMAT) has three components: hit time, miss rate, and miss penalty. For each of the following cache optimizations, indicate which component of the AMAT equation is improved. a. Using a second-level cache b. Using a direct-mapped cache C. Using a 4-way set-associative cache

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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5. The Average Memory Access Time equation (AMAT) has three components: hit time, miss rate, and miss penalty. For each of the following cache optimizations, indicate which component of the AMAT equation is improved. a. Using a second-level cache b. Using a direct-mapped cache C. Using a 4-way set-associative cache d. Using a non-blocking cache (While handling the cache miss, CPU can choose the right instruction to execute in no hazard by using Out-of-order CPU) e. Using larger blocks 6. Assume a CPU has • 1 memory bus clock to send the address • 10 memory bus clocks for each DRAM access initiated 1 memory bus clock to send a word of data a cache block = 8 words. What is the miss penalty of this CPU in following cases: a. A one-word-wide bank of DRAMS b. A four-word-wide bank of DRAMS C. A four-bank, one-word-wide bus of DRAMS
Transcribed Image Text:5. The Average Memory Access Time equation (AMAT) has three components: hit time, miss rate, and miss penalty. For each of the following cache optimizations, indicate which component of the AMAT equation is improved. a. Using a second-level cache b. Using a direct-mapped cache C. Using a 4-way set-associative cache d. Using a non-blocking cache (While handling the cache miss, CPU can choose the right instruction to execute in no hazard by using Out-of-order CPU) e. Using larger blocks 6. Assume a CPU has • 1 memory bus clock to send the address • 10 memory bus clocks for each DRAM access initiated 1 memory bus clock to send a word of data a cache block = 8 words. What is the miss penalty of this CPU in following cases: a. A one-word-wide bank of DRAMS b. A four-word-wide bank of DRAMS C. A four-bank, one-word-wide bus of DRAMS
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