A computer employs RAM chips of 512 × 8 and ROM chips of 128 × 8. The computer system need 1024 * 16 of RAM, 256 x 16 of ROM and two interface units with 256 registers each. a) Compute the number of chips required to realize the required memory b) Compute total number of decoders needed for the above system? c) Design a memory-address map for the above system d) Show the chip layout for the above design

A computer employs RAM chips of 512 × 8 and ROM chips of 128 × 8. The computer system need 1024 * 16 of RAM, 256 x 16 of ROM and two interface units with 256 registers each. a) Compute the number of chips required to realize the required memory b) Compute total number of decoders needed for the above system? c) Design a memory-address map for the above system d) Show the chip layout for the above design

Name: A computer employs RAM chips of 512 × 8 and ROM chips of 128 × 8. The
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Description: A computer employs RAM chips of 512 × 8 and ROM chips of 128 × 8. The computer system need1024 * 16 of RAM, 256 x 16 of ROM and two interface units with 256 registers each.a) Compute the number of chips required to realize the required memoryb) Compu

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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A computer employs RAM chips of 512 x 16 and ROM chips of 1024 x 8. The computer system needs 4K bytes of RAM and 2K bytes of ROM along with interface unit of 128 registers each. A memory mapped I/O configuration is used. The two higher order bits are assigned for RAM, ROM and interface as 00, 01 and 10 respectively. a) How many RAM and ROM chips are needed b) Design a memory-address map for the above system
A computer employs RAM chips of 512 x 16 and ROM chips of 1024 x 8. The computer system needs 4K bytes of RAM and 2K bytes of ROM along with interface unit of 128 registers each. A memory mapped I/O configuration is used. The two higher order bits are assigned for RAM, ROM and interface as 00, 01 and 10 respectively. •a. Compute total number of decoders are needed for the above system? •b. Design a memory-address map for the above system •C. Show the chip layout for the above design
You have been contracted to design a memory system for a computer. Assuming the processor has 20 address lines, determine the number of 16 KB memories that can be placed (without overlapping) in the memory space of a processor.
We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.
b) With the aid of a diagram, illustrate how Memory Address Register (MAR) and Memory Data Register (MDR) support the CPU in retrieving data from the RAM.
6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…
Assume that one 32-bit and two 16-bit microprocessors are to be interfaced to a system bus. The following details are given: All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt-driven IO, and DMA. All microprocessors have a 16-bit address bus. Two memory boards, each of 128 KBytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible. The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary, and do the following: a. Give the system bus specifications in terms of number and types of lines. b. Describe a possible protocol for communicating on the bus (i.e., read-write, interrupt, and DMA sequences). c. Explain how the aforementioned devices are interfaced to the system bus.
Assume that the microprocessor can directly address 1M with a and 8 data pins. The maximum RAM system can design by using the following RAM chips is. Size of RAM chip Number of Chips 2K × 4 6 4K × 4 7 1k × 4 512 × 8 5 10 a. 27k × 8 b. 26k × 8 c. None of them d. 24k × 8 e. 25k × 8
Design a memory map for a system with 64 K of memory space, a 16-bit address bus, and a 8-bit data bus. The system needs to meet the following design requirements: The system needs 20 K of RAM, organized in a contiguous block starting at address 0x1000 . The system needs RAM filling the memory range from 0xA000 to 0xCFFF (inclusive) Your design must be subject to the following constraints in terms of access to memory chips: You can use a maximum of two (2) 8 K×8 RAM chips. You can use a maximum of two (2) 4 K×8 RAM chips. You can use a maximum of two (2) 8 K×8 ROM chips. You can use a maximum of two (2) 4 K×4 ROM chips.
A computer employs RAM chips of 512 x 8 and ROM chips of 256 x 8. The computer system needs1K bytes of RAM, 2K bytes of ROM, and eight interface units, each with 2 registers. A memory-mapped1/0 configuration is used. The two highest-order bits of the 16 bit address bus are assigned 10 for RAM,11 for ROM, and 00 for interface registers.a. How many RAM and ROM chips are needed?b. Draw a memory-address map for the system.c. Give the address range in hexadecimal for RAM, ROM, and interface.
. A computer employs RAM chips of 512 x 8 and ROM chips of 256 x 8. The computer system needs1K bytes of RAM, 2K bytes of ROM, and eight interface units, each with 2 registers. A memory-mapped1/0 configuration is used. The two highest-order bits of the 16 bit address bus are assigned 10 for RAM,11 for ROM, and 00 for interface registers.a. How many RAM and ROM chips are needed?b. Draw a memory-address map for the system.c. Give the address range in hexadecimal for RAM, ROM, and interface please sir i need full ansewr with full details
Assume that one 32-bit and two 16-bit microprocessors are to be interfaced to a system bus. The following details are given: 1. All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt-driven IO, and DMA. 2. All microprocessors have a 16-bit address bus. 3. Two memory boards, each of 128 KBytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible. 4. The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary, and do the following:a. Give the system bus specifications in terms of number and types of lines. Describe a possible protocol for communicating on the bus (i.e., read-write, interrupt, and DMA sequences). Explain how the aforementioned devices are interfaced to the system bus.