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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Consider a computer system with a 64-bit logical address and 32-KB page size. Thesystem supports up to 4096 MB of physical memory. How many entries are there ineach of the following?a. A conventional single-level page table?b. An inverted page table?Consider an operating system using memory mapping on a page basis and using a single level page table. Assume that the necessary page table is always in memory. The system takes 200 ns to make a memory reference, how long does a paged memory reference take? Group of answer choices 400 ns (nanoseconds) 809.2 ms (microseconds) 200 ns (nanoseconds) 1638.4 ms (microseconds)
- 1. Consider a computer system with a 30-bit logical address and 4-KB page size. The systemsupports up to 512 MB of physical memory. How many entries are there in each of the following?Assume that each page table entry is 4 Bytes.c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? 2. Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address.Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes.a. How many frames are in the systems? How many pages in the virtual address space for aprocess?b. If a single-level page table is deployed, calculate the size of the page table for each process.c. Design a multilevel page table structure for this system to ensure that each page table can fitinto one frame. How many levels do you need? Draw a figure to show your page systemsSuppose you have a byte-addressable virtual address memory system with 32 virtual pages of 32 bytes each, and 8 page frames. Assuming the following page table, answer the questions below: | Page # | Frame # | Valid bit ||--------|---------|-----------|| 0 | 4 | 1 || 1 | 3 | 1 || 2 | - | 0 || 3 | 0 | 0 || 4 | 1 | 1 || 11 | 6 | 0 || 13 | 7 | 1 || 17 | - | 0 | a) How many bits are needed to address this virtual memory? b) What is the size of the Page field? c) What is the size of the Offset field? d) What is the size of the Page Frame field? e) What is the maximum number of the entries in this Page Table? f) What Physical address corresponds to the Virtual address 0x22? Answer should be in hexadecimal number. (if the address causes a page fault, answer as "page fault" with the proper reason) g) What Physical address corresponds to the…Suppose you have a byte-addressable virtual address memory system with 32 virtual pages of 32 bytes each, and 8 page frames. Assuming the following page table, answer the questions below: | Page # | Frame # | Valid bit ||--------|---------|-----------|| 0 | 4 | 1 || 1 | 3 | 1 || 2 | - | 0 || 3 | 0 | 0 || 4 | 1 | 1 || 11 | 6 | 0 || 13 | 7 | 1 || 17 | - | 0 |a) How many bits are needed to address this virtual memory? b) What is the size of the Page field? c) What is the size of the Offset field? d) What is the size of the Page Frame field?
- Consider a logical address space of 32 pages of 1024 words each, mapped onto a physical memory of 8 frames. How many bits are there in logical address and how many bits are there in physical address?Assume a 32-bit address system that uses a paged virtual memory, with a page size of 2 KB. Answer the following questions, assuming a virtual address 0x00030f40 A. What is the virtual page number (VPN) and the offset in binary for the given virtual address? B. How many virtual pages are there in the system?Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
- Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?A computer has a 32-bit virtual address space and 1024 byte pages. A page table entry takes 4 bytes. A multilevel page table is used because each table must be contained within a page. How many levels are required?Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?