A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address, similar to Marie). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory?

A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address, similar to Marie). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory?

Name: A digital computer has a memory unit with 24 bits per word.The instru
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: A digital computer has a memory unit with 24 bits per word.The instruction set consists of150 different operations. All instructions have an operationcode part (opcode) and anaddress part (allowing for only one address, similar to Marie).Each instru

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

Most Intel CPUs use the __________, in which each memory address is represented by two integers.
_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.
A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?
In the ________, memory addresses consist of a single integer.
The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?
A digital computer has a memory unit with 32 bits per word. The instruction set consists of 127 different operations. All instructions have an operation code part (opcode), and an address part (allowing for only one address). Each instruction is stored in one word of memory. How many bits are needed for the opcode? ________ How many bits are left for the address part of the instruction? _______ What is the maximum allowable size for memory? _________
In a computer instruction format, the instruction length is 16 bits, and the size of an address field is 4 Is it possible to have: 15 instructions with 3 addresses, 14 instructions with 2 addresses, 31 instructions with one address, and 16 instructions with zero addresses, using this format? Justify your answer.
Consider a word-addressable computer with 32 bits per word. The instruction set consists of 30 different All instructions have an operation code field, a mode field to specify one of 7 possible addressing modes, a register address field to specify one of 60 available registers, and a memory address field. Each instruction is stored in one word of memory. What is the maximum allowable size for memory? Use KB, MB, or GB as a unit.
Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
Q.1. A computer uses a memory unit with 1024 K words of 32 bits each (as shown in the figure below). A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part (15). How many bits are there in the operation code, the register code part, and the address part? Draw the instruction word format and indicate the number of bits in each part? How many bits are there in the data and address inputs of the memory?