(a) Draw pipeline diagram (FI, DI, FO, EI) with one memory port for the following instructions: MOV [1234], 035 ADD [1234], AX SUB BX, CX XOR CX, BX AND BX, 035 PUSH CX (b) Write the code for the following. Rewrite the code to reduce hazards by instruction rescheduling: [c]= [a] -[e] [b]= [c] + [d] [f] = [d] + [e]

(a) Draw pipeline diagram (FI, DI, FO, EI) with one memory port for the following instructions: MOV [1234], 035 ADD [1234], AX SUB BX, CX XOR CX, BX AND BX, 035 PUSH CX (b) Write the code for the following. Rewrite the code to reduce hazards by instruction rescheduling: [c]= [a] -[e] [b]= [c] + [d] [f] = [d] + [e]

Name: (a) Draw pipeline diagram (FI, DI, FO, EI) with one memory port for t
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: (a) Draw pipeline diagram (FI, DI, FO, EI) with one memory port for the following instructions:MOV [1234], 035ADD_[1234], AXSUB BX, CXXOR CX, BXAND BX, 035PUSH CX(b) Write the code for the following. Rewrite the code to reduce hazards by instruction

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

If the following code segment is pipelined, which are the instructions affected by data hazards and which are not? Justify your answer with appropriate explanations and a pipeline block diagram. ADD R1,R2,R3 MUL R2, R4,R5 AND R6,R2,R7 OR R8, R6, R4 XOR R9, R8,R3
b. Design and reflect on a suitable pipeline technique using which time taken for executing all 3 programs can be further improved. Calculate the improved time using this method by considering that instruction require same number of steps to complete and time taken for each step is same and time gap between each steps is also same?
2- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex. addi $t0, $Zero, -50 andi $t1, $t0, 7 Loop:and $t1,$t0,$t1 Sw $t0, 40 ($t1) Bne $t1,$ zero, Loop
CORRECT AND DETAILED ANSWER Assume that the contents in AX and BX are signed numbers and the contents in CX and DX are unsigned numbers. Please use a comparison instruction and a conditional transfer instruction to accomplish the following tasks. If the content in BX is larger than that in AX, transfer to execute the instruction with a label of EXCEED. If the content in BX is larger than or equal to that in AX, transfer to execute the instruction with a label of EXCEED.
2. For the following C statement, what is the corresponding MIPS assembly code? Assume that the C variables a, b, and c, have already been placed in registers $s0, $s1, $s2, respectively. Use a minimal number of MIPS assembly instructions. a = b + (c − 5); 3. For the following C statement, write the corresponding MIPS assembly code. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[i-j] = A[8]; 4.Translate the following C code to MIPS. Assume that the variables, f,g. h, i, and j are assigned to registers $s0, $s1, $s2, $s3, $s4, and $s4, respectively. Assume that the base address of A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 8-byte words: B[8] = A[i] + A[j]; 5.For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the…
Question 7: In the following instruction sequence, show the resulting value of AL where indicated, in Hexadecimal: a. mov al,7Ah not al ; . b. mov al,72h xor al,0DCh ; and also write instructions that first clear bit positions 0,1 and 2 in AL. Then, if the destination operand is equal to zero, the code should jump to label LABEL1. Otherwise, it should jump to label NEXT
- Show Instruction Pipeline architecture and evaluate the pipelined and non- pipelined architecture. Use diagrams to explain.
Chapter 5 - Instruction Set Architecture Design your own problem to explain the different addressing modes (do not copy an example from the textbook but you may base your problem on an exercise in the textbook). Focus on the Immediate, Direct, Indirect, Indexed (R1-based), and Register Indirect modes.
For the following MIPS assembly instructions what is the corresponding C statement? Assume that variables f,g,h,i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Add comments for each line to describe what each instruction does. addi $t0, $s6, 4 # $t0 = &A+4 = &A[1] add $t1, $s6, $zero # sw $t1, 0($t0) # lw $t0, 0($t0) # add $s0, $t1, $t0 #
(ASM) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[f] = A[(i-h)+j] + g;
Please solve and show all work. Thank you. For the following C statement, write a minimal sequence of MIPS assembly instructions that does the identical operation. Assume $t1 = A, $t2 = B, and $s1 is the base address of C, << is shift left operation. A = C[0] << 12;
Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing.