a) I, b) Vs y VDs c) V. y Vcs d) V, 18 V Ip 2 kn 750 k2 o Vo = 9 V VG Vas Inss =8 mA Vas V 91 k2 0.68 k2

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Given VD = 9 V for the configuration shown. Decide:

a) I,
b) Vs y VDS
C) VG y Vcs
d) V,
18 V
Ip
2 k
750 k2
o Vp = 9 V
VG
Vps
Ipss = 8 mA
+.
VGs V
91 k2
0.68 k2
Transcribed Image Text:a) I, b) Vs y VDS C) VG y Vcs d) V, 18 V Ip 2 k 750 k2 o Vp = 9 V VG Vps Ipss = 8 mA +. VGs V 91 k2 0.68 k2
Expert Solution
Introduction.

DC bias of a FET device needs a setting of gate-source voltage VGS to give the desired drain current ID. For a JFET drain current is limited by the saturation current IDS. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

The circuit given in the question is Fiin Fixed bias configuration.

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