A program sees a 4% miss rate on both the Instruction Cache and the Data Cache.Every instruction requires access to the Instruction cache.Only 35% of the instructions require data access from the Data Cache.The miss penalty for either the data or the instruction cache is 100 cycles.Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible).Assume the number of instructions in a program is X. F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache)F2: What is the number of 'data miss cycles'?F3: What is the total run time of the program including the missed cycles dues to data and instruction misses?

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Computer Networking: A Top-Down Approach (7th Edition)

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ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

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A program sees a 4% miss rate on both the Instruction Cache and the Data Cache.
Every instruction requires access to the Instruction cache.
Only 35% of the instructions require data access from the Data Cache.
The miss penalty for either the data or the instruction cache is 100 cycles.
Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible).
Assume the number of instructions in a program is X.

F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache)

F2: What is the number of 'data miss cycles'?

F3: What is the total run time of the program including the missed cycles dues to data and instruction misses?

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