a) Serially shifting a byte of data into a shift register. b) Parallel loading a byte of data into a shift register with a synchronous load. c) Parallel loading a byte of data into a shift register, then to serial out this byte.
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- Question 5 what if the cpu burst time is so big such as job 1 is 300, job 2 is 400 and job 3 is 392. how to find the number of interrupt in round robin. time quantum =10. assume arrival start for all is 0. ...q) How the operation of software interrupt instructions differs i.e. INT, INTO, INT 3, and BOUND? q) Dynamic RAM (DRAM) retains data for only a short period (usually 2–4 ms) creatingproblems for the memory system designer. What type of mechanism is required to overcome this problem in DRAMs? q) What are the three common methods of expanding the interrupt structure of themicroprocessor? Explain any one of them along with example.In a register/memory type CPU, the instruction lengths are typically variable. This presents a problem when the program is incremented during the Fetch-Decode-Execute cycle. What statements(s) is/are NOT TRUE with regard to Program Counter (PC) incrementing? Select one or more A. The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be calculated. B . PC is incremented by the largest possible foxed value, irrespective of the variability of the instruction C. Increment value is known when the current instruction has completed execution. D. increment value is known when the current instruction is decoded with the Instruction Register (IR) E. PC incrementing method is implementation dependent
- You are given snapshots of the MIPS pipeline from two successive cycles. For each figure, fill in all the relevant information in each stage, corresponding to the instruction in that stage at that cycle. Remember to specify clearly how control signals are set. Assume $x contains x * 100 (e.g. $1 contains 100). MIPS instructions used: add rd, rs, rt rd = rs + rt or rd, rs, rt rd = rs or rt lw rt, I(rs) rt = Mem[rs + I] (load word) sw rt, I(rs) Mem[rs + I] = rt (store word)If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Problem Given the following memory values and a one-address machine with an accumulator, what values do the following instructions load into the accumulator? Word 20 contains 40. Word 30 contains 50. Word 40 contains 60. Word 50 contains 70. LOAD IMMEDIATE 20 LOAD DIRECT 20 LOAD INDIRECT 20 LOAD IMMEDIATE 30 LOAD DIRECT 30 LOAD INDIRECT 30
- We mentioned that a large volume of data is gathered during system probe traces. To give you some idea of the actual volume of data involved, suppose plans are being made to install a hardware probe that reports the contents of a system’s program counter, instruction register, accumulator, memory address register, and memory buffer register. The system has a clock that runs at 1GHz. During each cycle of the system clock, the status of these five registers is written to nonvolatile memory attached to the probe circuitry. If each register is 64 bits wide, how much storage will the probe require if it is to gather data for 2 seconds?b) Machine cycle defines a loop process with four major components. Explain why machine cycle is important? If the components of machine cycle are inter-swapped, would that cause any problems? Can we add another module to rectify the problem caused by inter-swapping? c) Cache memory and RAM both are based on transistor based then why cache memory is needed if we already have RAM (Random Access Memory) as a volatile memory? Is it possible to deploy any one type of memory in computer for all purposes?Explain each of the following.a. What is an interrupt?b. What interrupts the CPU?c. When does the CPU check for an interrupt?d. What does the CPU do to handle the interrupt?e. Of the four forms of I/O, programmed, interrupt-driven, DMA and channel, which use(s) interrupts so that the CPU can physically move the input/output datum?f. Of the four forms of I/O, which form(s) use interrupts (but not in the same way)?
- Install new interrupt # 76h that do the following: Compare the value of registers AX and BX. if AX> BX then it will print 1 if AX<BX then it will print 2 if AX = CX then it will print 3 All the best, Example: After you install the new interrupt, go to debug - A 100 mov ax, 6 mov bx,6 int 76h - g=100 the output will be 3 (because ax = bx). in assembly language6. Fill in the requested register values on the right side of the following instruction sequence:mov esi,OFFSET myBytesmov ax,[esi] ; a. AX =mov eax,DWORD PTR myWords ; b. EAX =mov esi,myPointermov ax,[esi+2] ; c. AX =mov ax,[esi+6] ; d. AX =mov ax,[esi-4] ; e. AX =Help for the question.Question 5a) For the single-cycle processor, what are the values (in binary) of instruction[31-26], instruction[25-21], instruction[20-16], instruction[15-11], instruction[5-0], Read data 1, Read data 2, ALU zero, PCSrc, and all the main control decoded output signals when the time is at 1950 ns. The figure of processor can be use.Then fill in the following. At the moment of 1950 ns, the below values (0, 1 or X) are:instruction[31-26] = instruction[25-21] = instruction[20-16] = instruction[15-0] = Read data 1 output = Read data 2 output = MemWrite = Branch = ALUop[1:0] = ALU zero = PCSrc = RegDst = ALUSrc = MemtoReg = RegWrite = MemRead =