a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this ne CPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below? R-type/I-Type LDUR STUR CBZ B 52% 25% 10% 11% 2%

Database System Concepts
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ISBN:9780078022159
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Chapter1: Introduction
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(a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this new
CPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below?
LDUR
STUR
CBZ
B
25%
10%
11%
2%
R-type/I-Type
52%
Transcribed Image Text:(a) Suppose you could build a CPU where the clock cycle time was different for each instruction. What would the speedup of this new CPU be over the CPU presented in COD Figure 4.23 (The simple control and datapath...) given the instruction mix below? LDUR STUR CBZ B 25% 10% 11% 2% R-type/I-Type 52%
Figure 4.4.10: The simple control and datapath are extended to handle the unconditional branch
instruction (COD Figure 4.23).
An additional OR-gate (at the upper right) is used to control the multiplexer that chooses between the branch target and the sequential
instruction following this one. One input to the OR-gate is the Uncondbranch control signal. Although not shown, the Sign-extend logic
would recognize the unconditional branch opcode and sign-extend the lower 26 bits of the branch instruction to form a 64-bit address to
be added to the PC.
PC
4-
>Add
Read
address
Instruction
[31-0]
Instruction
memory
Instruction [31-21]
Instruction [9-5]
Instruction [20-16]
Instruction [4-0]
Control
Instruction [31-0]
Reg2Loc
Uncondbranch
Branch
MemRead
MemtoReg
ALUOP
MemWrite
ALUSrc
RegWrite
hogy
Read
register 1 Read
data 1
Read
register 2
32
Read
Write
register data 2
Write
data Registers
Sign-
extend
64
Instruction [31-21]
Shift
left 2,
MSX
ALU
Add result
Zero
ALU ALU
result
ALU
control
Address
Read
data
Write Data
data memory
Transcribed Image Text:Figure 4.4.10: The simple control and datapath are extended to handle the unconditional branch instruction (COD Figure 4.23). An additional OR-gate (at the upper right) is used to control the multiplexer that chooses between the branch target and the sequential instruction following this one. One input to the OR-gate is the Uncondbranch control signal. Although not shown, the Sign-extend logic would recognize the unconditional branch opcode and sign-extend the lower 26 bits of the branch instruction to form a 64-bit address to be added to the PC. PC 4- >Add Read address Instruction [31-0] Instruction memory Instruction [31-21] Instruction [9-5] Instruction [20-16] Instruction [4-0] Control Instruction [31-0] Reg2Loc Uncondbranch Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite hogy Read register 1 Read data 1 Read register 2 32 Read Write register data 2 Write data Registers Sign- extend 64 Instruction [31-21] Shift left 2, MSX ALU Add result Zero ALU ALU result ALU control Address Read data Write Data data memory
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