Assume a classical RISC pipeline with regular (not delayed) branches. This pipeline has five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute Instruction (EX), Memory Access (MEM), and Writeback (WB). You may assume that there are no resource hazards in this pipeline, but data hazards may exist. Draw a timing diagram that shows the execution of the following instructions in this pipeline. Assume that R1, R2, etc. are registers while A, B, etc. are memory operands. The first operand is the destination while the second operand is the source. The numbers on the left are the addresses of the instructions. BRA is an unconditional branch to a target address 120.