Assume a five-stage single pipeline (IF, ID, EX, MEM, and WB) microarchitecture. Given the following code, Loop: Iw r3, 0(r0) Iw r1, 0(r3) daddi r1, r1, 1 dsub r4, r3, r2 sw r1, 0(r3) bnz r4, loop a) Draw the pipeline diagram of one iteration of the code, and report the cycle per instruction (CPI); b) Please show all dependencies

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