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- We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.The faster memory of the memory hierarchy costs the most amount of money. Given this fact, which of the following is fastest and the most costly? A) RAM B) registers C) cache D) virtual memory secondary storageAssume a CPU with a fixed 32-bit instruction length has the following instruction format:opcode mode [operand1] [operand2] [operand3]The mode encodes the number of operands and each operand’s mode. For instance, one mode indicates three registers, another indicates two registers and an immediate datum, another indicates a main memory reference, etc. Assume there are 94 instructions and 22 modes. Answer the following.a. One mode indicates three registers. How many registers can be referenced in this mode?b. One mode indicates two registers and an immediate datum in two’s complement. Assuming there are 32 registers, what is the largest immediate datum that can be referenced?c. One mode has a destination register and a source memory address (an unsignednumber). Assuming 16 registers, what is the largest memory reference available?d. One mode has two memory addresses, both using base displacement. In both, the basesare stored in index registers and the displacements are specified in the…
- AssemblyWhat does "align 8,5" mean? Draw the data memory layout of the data memory starts at 0x20000000Area myData, DataAlign 4a DCB 1b DCB 2c DCB 3Align 8,5d DCB 5How does memory coalescing improve memory access efficiency in GPU (Graphics Processing Unit) memory systems, and what types of workloads benefit the most from this technique?You are participating in a Hackathon and you have been assigned a task to add a module to a newly built microprocessor that finds the volume of a sphere given the radius. Device an assembly code using 0-address, 1-address and 2-address instruction format that does this task. Explain each instruction clearly to achieve the final result
- Memory address translation is useful only if the total size of virtual memory (summed over all processes) needs to be larger than physical memory. True or False. Justify your answer.Take the multiprocessor with 30 processors, each processor is capable od max 2Gflops. What is the maximum capability of the multiprocessor for the execution of an application that has 5% sequential code? Use Amdahl's lwWe want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.
- What are the inadequacies of the Whetstone, Dhrystone, and Linpack benchmarks that the SPEC CPU benchmarks address?Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.1. Which is the correct path that a CPU follows for loading data? a.cache → register → main memory → hard drive b.hard drive → main memory → cache → register c.hard drive → register → main memory → cache d. register → cache → main memory → hard drive