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- A computer system has a memory access time of 11.0 ns and is using a SATA III SSD (solid state drive) capable of transferring 8 Gbit/s. The size of a page is 1024 bytes. What should the probability of a page fault be so that access time degradation does not exceed 14%?A computer has four page frames. The time of loading, time of last access, and the R and M bits for each page are as show (the times are in clock ticks): Page Loaded Last ref. R M 0 126 280 1 0 1 230 265 0 1 2 140 270 0 0 3 110 285 1 1 At the time of page fault which page will be replaced by following algorithms: 1. FIFO 2. LRU 3. Second chanceThe overhead required to read an entry in a page table (including the time to access TIB) is 60 nanoseconds. To reduce this overhead, the computer has a TIB that can hold 16 entries and be accessed in 10 nanoseconds.a) Let B = TLB lookup time, T - memory cycle time, and p = hit ratio. Finda formula that expresses the effective access time.b) What hit ratio is needed to reduce the effective access time to 70 nanoseconds?
- A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…Assume a computer has on-chip and off-chip caches, main memory and virtual memory. Assume the following hit rates and access times: on-chip cache 95%, 1 ns, off-chip cache 99%, 10 ns, main memory: X%, 50 ns, virtual memory: 100%, 2.5 ms. Assume that an acceptance effective access time is 1.6 ns. What should X be (the percentage of page faults) to ensure that EAT is no worse than 1.6 ns?
- Thefollowing page addresses, in the given sequence,were generated by a program: 1 8 3 4 8 1 5 6 8 1 8 3 7 6 3 8 1 8 3 6 Calculate the page faults using below page replacementalgorithms for memory with3 and 5 framesseparately. Assume that the main memory is empty initially. (a) LRU (b) FIFO (c) Optimal Page Replacement (d) Which is the most efficient among them and why?This problem studies the effect of changing page sizes in a demand paging system. The following sequence of requests for program words is taken from a 460-word program: 10, 11, 104, 170, 73, 309, 185,245,246,434,458, and 364. Main memory can hold a total of 200 words for this program, and the page frame size will match the size of the pages into which the program has been divided. Calculate the page numbers according to the page size; divide by the page size, and the quotient gives the page number. The number of page frames in memory is the total number, 200, divided by the page size. For example, in problem (a) the page size is 100, which means that requests 10 and 11 are on Page 0, and requests 104 and 170 are on Page 1. Therefore, the number of page frames is two. a.) Find the success frequency for the request list using a FIFO replacement Algorithm and a page size of 100 words (there are two page frames). b.) Find the success frequency for the request list using a FIFO…As we have seen, a potential drawback of SSDs is that the underlying flash memory can wear out. For example, for the SSD in (Figure 1), Intel guarantees about 128 petabytes (128×1015128×1015 bytes) of writes before the drive wears out. Given this assumption, estimate the lifetime (in years) of this SSD for the following workloads: Worst case for sequential writes: The SSD is written to continuously at a rate of 470 MB/sMB/s (the average sequential write throughput of the device). Express your answer as an integer. Worst case for random writes: The SSD is written to continuously at a rate of 303 MB/sMB/s (the average random write throughput of the device). Express your answer as an integer. Average case: The SSD is written to at a rate of 20 GB/dayGB/day (the average daily write rate assumed by some computer manufacturers in their mobile computer workload simulations). Express your answer as an integer.
- Consider the following set of processes, with the length of the CPU burst and I/O burst given in milliseconds: Process CPU, I/O, CPU Arrival time P1 2, 3, 1 0 P2 2, 1, 4 4 P3 1, 1, 4 10 P4 6, 6, 6 13 For example: In FCFS a process p1 arrived at 0 ms gets CPU for 2 ms, then releases CPU to the next process for 3ms where it performs I/O burst and return back to the queue with a new arrival time as (2+3 = 5ms) 5 ms. In case of a tie, go with process number. Perform the following for FCFS and non-preemptive SJF scheduling algorithm: Calculate the average waiting time, average turnaround time. With respect to each metric justify which scheduling algorithm is good for the given process mix.Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this caseGiven 512KB of memory, show the memory partitioning and allocation in a buddy system for the following requests. 50K, 228K, 56K, 4K, 2K, 1K, 3K