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- How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?Most Intel CPUs use the __________, in which each memory address is represented by two integers.97. During execution how many interrupts are made per block? a. one b. two c. three d. four
- Computer Organization and ArchitectureAssignment Submit your work by uploading it in Blackboard or bringing it as a hard copy to my office by the deadline. Answer the following question:1-What is the datapath?2-What is the Instruction cycle?3-What is the memory hierarchy? 4-Give small description or example and indicate the format of the following MIPS functions:(The first two of them are examples) Please here is three columns one to instructions and two to format of instruction and three column is to description of function to all instructions but i don't copy to here only Please solve it. FormatFormatDescription lw $1,100($2)Iload word from $2+100 and put it in $1 and $1,$2,$3Gadd $2 and $3 and put the result in $1 | $1= $2+$3 Sw $1,100($2) la $1,label andi $1,$2,100 or $1,$2,100 srl $1,$2,10 li $1,100 move $1,$2 Beq $1,$2,100 Bne $1,$2,100 div $2,$3 Bgt $1,$2,100 addi $1,$2,100 addu $1,$2,$3The term Parallel Run refers to A. the same job run on two different computer to test their speeds B. the processing of two different jobs initiated from two terminals. C. the concurrent operation of an existing system and a new system D. All of the above E. None of the above20. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged a. A hardware interrupt is needed b. A software interrupt is needed c. Either a or b d. A non-privileged instruction (which does not generate an interrupt)is needed
- Answer only (e,f,g, h, i) questions. (e) List the elements of the execution unit.(f) What is the highest and the lowest address in the 8086’s memory address space.(g) Is memory in the 8086 microprocessor organized as byte, words or double words ?(h) What is the value of the double word stored in memory starting at address B000316 if the contents ofmemory location B000316, B000416, B000516 and B000616 are 1116, 2216, 3316 and 4416 respectively ?i) What is the function of the stack?Memory address translation is useful only if the total size of virtual memory (summed over all processes) needs to be larger than physical memory. True or False. Justify your answer.q) How the operation of software interrupt instructions differs i.e. INT, INTO, INT 3, and BOUND? q) Dynamic RAM (DRAM) retains data for only a short period (usually 2–4 ms) creatingproblems for the memory system designer. What type of mechanism is required to overcome this problem in DRAMs? q) What are the three common methods of expanding the interrupt structure of themicroprocessor? Explain any one of them along with example.
- You have been tasked with developing a boot-loader that will be executed when the CPU is powered on. What attribute of the CPU should you investigate that will help you determine where the boot-loader code should be placed in the system's non-volatile storage? a. reset vector address b. the amount of cache c. location of the program counter d. internal clock speed113. The term Parallel Run refers to a. processing of two different jobs initiated from two terminals b. concurrent operation of an existing system and a new system c. the same job run on two different computers to test their speeds d. all of thesemicroprocessor 8086/8088 which one and how ? Assume the content of the segment register ES = ACEE H, the possible value for segment register CS= ? CS=B822H CS=A215H CS-ACEEH CS=2ED5H