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Back in the days, main memory modules used to be quite small in size. One such a module was of size 4 MB, which was connected to a processor with a direct mapped cache that could hold 64 KB of data. Both the main memory and cache had a block size of 4 words. a) If both the main memory and the cache were byte addressable, what could have been the minimum size of the physical memory address used for addressing both the main memory and the cache? b) What could have been the size of “tag" for addressing cache? c) Based on you answers to parts a and b, what should have been the total size of the direct mapped cache if each cache block contained an additional valid bit?

Back in the days, main memory modules used to be quite small in size. One such a module was of size 4 MB, which was connected to a processor with a direct mapped cache that could hold 64 KB of data. Both the main memory and cache had a block size of 4 words. a) If both the main memory and the cache were byte addressable, what could have been the minimum size of the physical memory address used for addressing both the main memory and the cache? b) What could have been the size of “tag" for addressing cache? c) Based on you answers to parts a and b, what should have been the total size of the direct mapped cache if each cache block contained an additional valid bit?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Back in the days, main memory modules used to be quite small in size. One such a module was of size 4 MB, which was connected to a processor with a direct mapped cache that could hold 64 KB of data. Both the main memory and cache had a block size of 4 words. a) If both the main memory and the cache were byte addressable, what could have been the minimum size of the physical memory address used for addressing both the main memory and the cache? b) What could have been the size of “tag" for addressing cache? c) Based on you answers to parts a and b, what should have been the total size of the direct mapped cache if each cache block contained an additional valid bit?
Transcribed Image Text:Back in the days, main memory modules used to be quite small in size. One such a module was of size 4 MB, which was connected to a processor with a direct mapped cache that could hold 64 KB of data. Both the main memory and cache had a block size of 4 words. a) If both the main memory and the cache were byte addressable, what could have been the minimum size of the physical memory address used for addressing both the main memory and the cache? b) What could have been the size of “tag" for addressing cache? c) Based on you answers to parts a and b, what should have been the total size of the direct mapped cache if each cache block contained an additional valid bit?
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