4 Consider a microprocessor that has a block I/O transfer instruction such as that foundon the Z8000. Following its first execution, such an instruction takes five clock cyclesto re-execute. However, if we employ a nonblocking I/O instruction, it takes a total of20 clock cycles for fetching and execution. Calculate the increase in speed with theblock I/O instruction when transferring blocks of 128 bytes.5 A system is based on an 8-bit microprocessor and has two I/O devices. The I/O con-trollers for this system use separate control and status registers. Both devices handledata on a 1-byte-at-a-time basis. The first device has two status lines and three controllines. The second device has three status lines and four control lines.a. How many 8-bit I/O control module registers do we need for status reading andcontrol of each device?b.What is the total number of needed control module registers given that the firstdevice is an output-only device?

Name: 4 Consider a microprocessor that has a block I/O transfer instruction
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Description: 4 Consider a microprocessor that has a block I/O transfer instruction such as that foundon the Z8000. Following its first execution, such an instruction takes five clock cyclesto re-execute. However, if we employ a nonblocking I/O instruction, it ta

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Engineering

Computer Science

Consider a microprocessor that has a block I/O transfer instruction such as that found on the Z8000. Following its first execution, such an instruction takes five clock cycles to re-execute. However, if we employ a nonblocking I/O instruction, it takes a total of 20 clock cycles for fetching and execution. Calculate the increase in speed with the block I/O instruction when transferring blocks of 128 bytes.

Consider a microprocessor that has a block I/O transfer instruction such as that found on the Z8000. Following its first execution, such an instruction takes five clock cycles to re-execute. However, if we employ a nonblocking I/O instruction, it takes a total of 20 clock cycles for fetching and execution. Calculate the increase in speed with the block I/O instruction when transferring blocks of 128 bytes.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 3PE: Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
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