Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i ≤ 1) {11, 12, 13, 14) where i = 0. Time(ns) taken by the instruction 11 to 14 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 11 1 1 2 1 1 12 1 2 1 1 1 13 1 2 2 1 1 14 2 1 2 1 1 The output of 14 will be available after

Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i ≤ 1) {11, 12, 13, 14) where i = 0. Time(ns) taken by the instruction 11 to 14 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 11 1 1 2 1 1 12 1 2 1 1 1 13 1 2 2 1 1 14 2 1 2 1 1 The output of 14 will be available after

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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The runtimes of the five stages of executing an instruction in a non-pipelined machine are listed below. Instruction Fetch 100ps Instruction Decode 200ps ALU 300ps Memory 300ps Write Back 200ps This is then converted into a pipelined machine M1 using the most critical stage as the cycle time. For a new machine M2, we are allowed to break up exactly one stage into two substages of equal times giving us a six stage pipeline. A1: Discuss in short clear sentences the latency differences between the machines M1 and M2. A2: Discuss in short clear sentences the throughput differences between the machines M1 and M2.
Consider the fragment of MIPS assembly below: sd $s5, 12($s3) Id $s5, 8($s3) sub $s4, $s2, $s1 beqz $s4, label add $s2, $s0, $s1 sub $s2, $s6, $s1 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. Draw a pipeline diagram to show were the code above will stall.
Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.
A CPU has an instruction pipeline with the following 4 segments. 1.F1(Fetch Instruction) 2.DA(Decode, Address) 3.FO(Fetch Operand) 4.EX(Execution) D1: Add R1,R2 //R1=R1+R2 Add R4,R1 //R4=R4+R1 Add R4,R3 //R4=R4+R3 Cmp R4,R5 // compare R4 and R5 Jg D1 //if Jump Greater (if R4>R5) Sub R2,R1 //R2=R2-R1 Sub R2,R3 //R2=R2-R3 Jmp D1
Consider the following portions of three different programs running at the same time on three processors in a symmetric multicore processor (SMP). Assume that before this code is run, W is 10, X= 50, Y=15, Z=5. Core 1: Total = W+ X;Core 2: Total = W - Y;Core 3: Total = W + Z; b) What are all the possible resulting values of Total? For each possible outcome, explain how we might arrive at those values. You will need to show all possible interleavings of instructions. c) How could you make the execution more deterministic so that only one set of values is possible?
When we execute such a program:(1) R1 = 3 + 5(2) R2 = R1 / 4(3) R3 = 4 * 16(4) R4 = R3 * 2We realize a problem in the pipeline of Teletraan-2. Instruction (2) will be waiting for the resultgenerated by Instruction (1). That means the operand fetch stage cannot fetch the operand ofInstruction (2) from R1, unless the write back stage finishes writing the result of Instruction (1)into R1. As a result, the pipeline is stalled for 3 CPU clock cycles. What should we do toalleviate the problem?A. Nothing. We will have to let Instructions (2), (3), and (4) wait.B. We will put Instructions (2), (3), and (4) in a queue. The first instruction whose operandsare ready will be issued and executed. In this case, Instruction (3) will be the nextinstruction executed after Instruction (1).C. We will put Instructions (2), (3), and (4) in a queue. The first instruction whose operandsare ready will be issued and executed. In this case, Instruction (4) will be the nextinstruction executed after Instruction…
We have a program of 10^6 instructions in the format of “lw,add,lw,add,…”. The add instruction depends only on the lw instruction right before it. The lw instruction also depends only on the add instruction right before it. If this program is executed on the 5-stage MIPS pipeline: a) Without forwarding, what would be the actual CPI? b) With forwarding, what would be the actual CPI
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?
Follow this steps. Have to Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.
Consider the two back to back instructions: lw $s1, 24($t3) add $t2, $s1, $t1 In the standard five stage, pipelined machine, consider the above two instructions where the second instruction tries to read a register that is being written to by the first instruction which is a 'load word' (lw) command. The scheduler has not done any juxtaposing of the commands. a. There will be no hazard situation as the load word deals with the data memory and the read is from the registers. b. There will be no hazard situation, since the read is from the same location where the write is taking place. c. It is possible to avoid a bubble in the flow by forwarding from the write back stage. d. It is not possible to avoid Data Hazard issues here and inserting a bubble is a way out of this issue.
Consider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)