Consider a system with 256Mbytes of main memory with page ize of 4Kbytes. It has a logical address space of 26-bits. Answer the following questi Assume byte-addressable memory) i) How many of the 26-bits of the logical address represent page# and how many bits epresent the offset? ii) How many entries are there in a conventional single-level page table for a process iii) How many entries are there in an inverted page table?
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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?Consider a system with 256Mbytes of main memory with page size of 4Kbytes. It has a logical address space of 26-bits. Answer the following questions. (Assume byte-addressable memory) (i) How many of the 26-bits of the logical address represent page# and how many bits represent the offset? (ii) How many entries are there in a conventional single-level page table for a process? (iii) How many entries are there in an inverted page table?Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?
- . Suppose we have 2 bytes of virtual memory and 28 bytes of physical main memory. Suppose the page size is 24 bytes.Q.) How many entries are in the page table for a process that uses all of virtual memory?Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? a.How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels is needed? Draw a figure to show your page systems;Suppose, a primary memory size is 56 bytes and frame size is 4 bytes. For a process with 20 logical addresses. Here is the page table which maps pages to frame number. 0 - 5 1 - 2 2 - 13 3 - 10 4 - 9 Then find the corresponding physical address of 12, 0, 9, 19, and 7 logical address.
- For the following two questions assume that a computer uses a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of size 8 bytes. Assume pages of size 16 bytes and a main memory of 4 frames. Assume the following TLB and page table for Process P: TLB 0 3 4 1 Page Table Frame Valid 0 3 1 1 0 1 2 - 0 3 2 1 4 1 1 5 - 0 6 - 0 7 - 0 Question 11 Show the address format for virtual address 0x43. Page Offset Question 11 options: Question 12 What physical address will be used for virtual address 0x12. Frame OffsetSuppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?Consider an operating system using memory mapping on a page basis and using a single level page table. Assume that the necessary page table is always in memory. The system takes 200 ns to make a memory reference, how long does a paged memory reference take? Group of answer choices 400 ns (nanoseconds) 809.2 ms (microseconds) 200 ns (nanoseconds) 1638.4 ms (microseconds)
- Suppose we have 210 bytes of virtual memory and 28 bytes of physical main memory. Suppose the page size is 24 bytes. a) How many pages are there in virtual memory? b) How many page frames are there in main memory? c) How many entries are in the page table for a process that uses all of virtual memory?Suppose a computer system uses 16 but addresses for both virtual and physical address. In addition, assume each page (and frame) has a size of 256 bytes. -How many bits are used for page number? -How many bits for offset? -what is the max number of pages a process can have?Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.Q.) What is the format of a memory address as seen by the cache; that is, what are the sizes of the tag and offset fields?