Consider the following sequence of instructions: add $t0, $t1, $t2 sub $t3, $t0, $t3 Iw $t5, 0($t0) beq $t5, $t6, BRANCH Q1: Analyze the data dependence in the given instruction sequence. Dependence?(Which $ is depend on which $? Type?) add $t0, $t1, $t2 NA sub $t3, $t0, $t3 Iw $t5, 0($t0) beq $t5, $t6, BRANCH Q2: If we assume ideal 5-stage pipelining (i.e., no hazards and therefore no stalls), how many cycles are needed to execute the code above? [Assuming each instruction takes 5 cycles to finish] Q3: If we now assume a more realistic pipelined datapath without forwarding, show a revised code sequence that includes all necessary nops instructions. Then, how many cycles are needed to execute the code?

Consider the following sequence of instructions: add $t0, $t1, $t2 sub $t3, $t0, $t3 Iw $t5, 0($t0) beq $t5, $t6, BRANCH Q1: Analyze the data dependence in the given instruction sequence. Dependence?(Which $ is depend on which $? Type?) add $t0, $t1, $t2 NA sub $t3, $t0, $t3 Iw $t5, 0($t0) beq $t5, $t6, BRANCH Q2: If we assume ideal 5-stage pipelining (i.e., no hazards and therefore no stalls), how many cycles are needed to execute the code above? [Assuming each instruction takes 5 cycles to finish] Q3: If we now assume a more realistic pipelined datapath without forwarding, show a revised code sequence that includes all necessary nops instructions. Then, how many cycles are needed to execute the code?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a generic processor executing the following set of machine instructions. Memory location 34 contains a value 20. What statement best express the final outcome? MOV R1, #0 MOV R2, #34 MOV R3, #1034 ADD R1, (R2) MOV (R3), R1 Select one or more A. memory location 20 contains value 1034 B.memory location 1034 contains value 54 C. memory location 1034 contains value 34 D. memory location 20 contains value 34 E. memory location 1034 contains value 20
do { flag[i] = true; turn = i; while (flag[j] && turn == j); Critical section flag[i] = FALSE; Remainder section } Three processes P1, P2, and P3 are sharing a resource R1 in a mutually exclusive manner. Using compare_and_swap instruction, show code for P1, P2, and P3 that shows the entry section and exit section (similar to the code shown in Question 1). Using this code, show a scenario if all three processes want to enter their critical sections.
Suppose that the registers $t1 and $t2 contain the following values: $t1: 0100 1101 0000 0000 0101 0111 0101 0110 $t2: 0010 0100 0110 1000 0010 0110 0011 0011 What is the value of $t3 after executing these instructions? sll $t1, $t1, 4 andi $t3,$t1, $t2 srl $t3, $t3, 3
Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? What fraction of all instructions use instruction memory? What fraction of all instructions use the sign extender?
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <§4.4>What fraction of all instructions use data memory? 4.3.2 [5] <§4.4>What fraction of all instructions use instruction memory? 4.3.3 [5] <§4.4>What fraction of all instructions use the sign extend? 4.3.4 [5] <§4.4>What is the sign extend doing during cycles in which its output is not needed?
In the Compare&Swap instruction, why must the instruction execute atomically? Write about: Busy waiting - is undesirable because it’s inefficient Potential starving of a process Deadlock - low priority process and high priority process are stuck Compare&Swap: // critical section based on // compare_and_swap instruction Shared variable x=0 while (true) { while (compare_and_swap(x, 0, 1) == 1) // do nothing // critical section code here x = 0; // remaining code… } // instruction logic int compare_and_swap(int *word, int testval, int newval) { int oldval; oldval = *word; if (oldval == testval) *word = newval; return oldval; }
Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.
Consider the code sequence below lw $t1, 4($t0) add $s2, $t1, $t2 lw $t3, 16($t0) add $s3, $t3, $t2 lw $t4, 28($t0) add $s4, $t4, $t2 Suppose there is no forwarding allowed, and for the result of a lw to be consumed by the following R-type of instruction requires 2 bubbles to be placed between the two instructions. Is it possible for the scheduler to juxtapose the commands in such a way that there is no need for any bubbles? If yes, give an example of how it can be done.
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
5. When two words are multiplied (one in BX), the most significant word of result will be in _______, and the least significant word will be in __________ (1 Mark) a. BX, CX b. CX, BX c. AX, DX d. DX, AX 6. Compare and contrast SUB and CMP instructions? (1 Mark) 7. Write the contents of AH and BL after execution of the program. (1 Mark) MOV AH,40h SAL AH, 01 MOV BL,80h SAR BL,01 HLT AH= ____________ BL= ____________ 8. Write the contents of AL and BL register after execution of the program (1 Mark) MOV AL, FFh MOV BL, AL CMP AL, F0H SUB BL,10H HLT AL= ____________ BL= ____________ 9. Identify and correct the mistakes. (1 Mark) MOV AX, 32H ____________________ MOV BL, 2424H ____________________ DAS AX, BL ____________________ HLT ____________________ 10. Write an ALP to rotate right the contents of AL register 4 times including carry and save the result in DH register (1 Mark)