Construct the truth table from the Below VHDL code for the decoder. library IEEE;use IEEE.STD LOGIC 1164 ALL;entity dec2to4 isPort ( enable : in STD LOGIC;sw : in STD LOGIC VECTOR (1 downto 0);led out STD LOGIC VECTOR (3 downto 0));end dec2to4;architecture Behavioral of dec2to4 isbeginled <="0000" when enable='0' else"0001" when sw="00" else"0010" when sw="01" else"0100" when sw="10" else"1000";end Behavioral:

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Construct the truth table from the Below VHDL code for the decoder.

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Question

Construct the truth table from the Below VHDL code for the decoder.

library IEEE;
use IEEE.STD LOGIC 1164 ALL;
entity dec2to4 is
Port ( enable : in STD LOGIC;
sw : in STD LOGIC VECTOR (1 downto 0);
led out STD LOGIC VECTOR (3 downto 0));
end dec2to4;
architecture Behavioral of dec2to4 is
begin
led <="0000" when enable='0' else
"0001" when sw="00" else
"0010" when sw="01" else
"0100" when sw="10" else
"1000";
end Behavioral:

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