D out1 D out2 CIk CIk CIk
Given the circuit, each two-input XOR gate has a propagation delay of 80 ps and a contamination delay of 40 ps and the NOT gate has a propagation delay of 30 ps and a contamination delay of 15 ps . Each flip-flop has a setup time of 80 ps, a hold time of 50 ps, a clock-to-Q propagation delay of 100 ps, and a clock-to-Q contamination delay of 40 ps.
Is the circuit satisfying the hold time constraint?
Assuming that we only care about the output at out2, what modification to the given circuit would you suggest so that the circuit satisfies hold constraint while the functionality at out2 remains unchanged? Draw your updated circuit below. You may (or may not) use an additional NOT gate apart from which no extra components are provided. You are free to move around the gates. What is the highest clock frequency you can use for the updated circuit? There is no one correct answer for this question, you can be creative as long as the output at out2 is correct. Please note that out2 changes three clock edges after the input changes, this needs to be maintained in your updated circuit as well.
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