Data is stored in memory as follows: Address M[X6] M[X6 + 8] M[X6 + 16] M[X6 + 24] Data 300 301 62 173 Using just LDR and STR, write ARM V8 assembly that will sort the data from lowest to highest (i.e., the smallest value should be in the smallest memory location). The base of the array is stored in register X6. You may use no more than nine lines, and you may not write to any memory address other than the above. Note: you do not need to write a general sort program. Just a block of code which will sort the particular data given!

1. T/F - if (B)=006000 (PC)=003600 (X)=000090, for the machine instruction 0x032026, the target address is 003000.2. T/F – PC register stores the return address for subroutine jump.3. T/F – S register contains a variety of information such as condition code.4. T/F – INPUT WORD 1034 – This means Operating system should reserve 1034 bytes in memory5. T/F - In a two pass assembler, adding literals to literal table and address resolution of local symbol are done using first pass and second pass respectively.

A computer architecture simulator is a program that simulates the execution of computer architecture. Run the simulator with the following MIPS assembly program .data array: .word 1, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37 sum: .word 0 # this location will contain the sum .text .globl main main: la $s0, array li $t1, 12 add $t2, $zero, $zero loop: addi $t1, $t1, -1 sll $t3, $t1, 2 add $t3, $s0, $t3 lw $t0, 0($t3) add $t2, $t2, $t0 bne $t1, $zero, loop exit: la $s0, sum sw $t2, 0($s0) Write a report to describe the assembly program with a comment for each instructor, the comment need to describe the instruction types (data movement, data manipulation, control, etc.), address mode used (direct, indirect, register direct, register indirect, displacement, immediate) and the role for each register used. Also attach a set of full screen shots with time stamps to show the simulations characteristics and results.

1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.

A 32-bit computer has a data cache memory with 8 KB and lines of 64 bytes. Calculate the hit ratio of this program. double a[1024], b[1024], c[1024], d[1024]; // A double occupies 8 bytes , // the array are consecutively stored // in memory for (int i = 0; i < 1024; i++) a[i] = b[i] + c[i] +d[i];   The cache uses a direct mapped function and write-back policy. The cache uses a full associative cache with LRU as replacement algorithm. The cache uses a 2-way associative cache and a 4-way associative cache with LRU as replacement algorithm.

Suppose a computer using direct mapped cache has 4M byte of byte-addressable main memory, and a cache of 512 blocks, where each cache block contains 64 bytes.  a) How many blocks of main memory are there?  b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields?  c) To which cache block will the memory address 0x00007266 map?

instruction is in the first picture please give me only implementation of int L1lookup(u_int32_t address) and int L2lookup(u_int32_t address) cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0…

1- Write an X86 assembly program that searches through a block of 100H characters starting from data segment memory location BLOCKA. This program must count all lower-case letters and all upper-case letters. Byte-sized data segment memory location LOWER must contain the count of small letters, and data segment location UPPER must contain the count of capital letters. 2- Write an X86 assembly program that copies the contents of the previous byte-sized memory block (BLOCKA) into a new byte-sized memory block (BLOCKB) after converting the case of the letters taking into account the block BLOCKA ends with the symbol #. Hint:  Use your name, ID No. and your points in our previous assignments and terminates the string using the character ‘#’ as follows: BLOCKA db ‘nAME sURNAME  id nO. 16-155-777 aSSG1=90, aSSG2=100, aSSG3=60 sPRING 2020 #’

Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.                                           a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x01D872 map?

3.0  Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit hexadecimal memory addresses, given as byte addresses. 74, A0, 78, 38C, AC, 84, 88, 8C, 7C, 34, 38, 13C, 388, 18C 3.0.1     For each of these references, identify the index and the tag, given a direct-mapped cache with 8 one-word blocks. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier. 3.0.2      For each of these references, identify the index and the tag, given a direct-mapped cache with two word blocks and a total of 16 words. List if each reference is a hit or a miss, assuming the cache is initially empty and show every entry to the cache, including the tag value and the addresses of all data items stored. Use hexadecimal or binary, whichever is easier.