Disabling interrupt synchronization involves re-enabling it before leaving a critical region. Assume one CPU disables interruptions after reaching a vital location and another CPU's interrupt enable flag is set to 0. P2 wants to reach the crucial area with any CPU. What may happen?

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
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Disabling interrupt synchronization involves re-enabling it before leaving a critical region. Assume one CPU disables interruptions after reaching a vital location and another CPU's interrupt enable flag is set to 0. P2 wants to reach the crucial area with any CPU. What may happen?

 

 

 

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