Draw the timing diagram for the inputs (M, A, B) in the test bench of 4. In this diagram, show the values of signals A and B as hexadecimal numbers.
Draw the timing diagram for the inputs (M, A, B) in the test bench of 4. In this diagram, show the values of signals A and B as hexadecimal numbers.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![module add_sub_4bits_tb();
reg [3:0] A, B;
reg M;
wire [3:0] S;
wire [4:1] C;
add_sub_4bits UUT (A, B, M, S, C);
initial begin
M=0;
A=4'b0000;
B=4'b0100;
end
initial begin
repeat (7) #100 A=A+4'b0001;
#100 M=1;
#100 A=4'b0000;
repeat (7) #100 A=A+4'b0001;
end
endmodule
Draw the timing diagram for the inputs (M,
A, B) in the test bench of 4. In this diagram,
show the values of signals A and B as
hexadecimal numbers.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F4620f1dc-ca23-460d-913d-2f41705d169e%2Fade1023f-7fa2-4cce-b8e7-30c089ee920e%2Fdktk5x_processed.jpeg&w=3840&q=75)
Transcribed Image Text:module add_sub_4bits_tb();
reg [3:0] A, B;
reg M;
wire [3:0] S;
wire [4:1] C;
add_sub_4bits UUT (A, B, M, S, C);
initial begin
M=0;
A=4'b0000;
B=4'b0100;
end
initial begin
repeat (7) #100 A=A+4'b0001;
#100 M=1;
#100 A=4'b0000;
repeat (7) #100 A=A+4'b0001;
end
endmodule
Draw the timing diagram for the inputs (M,
A, B) in the test bench of 4. In this diagram,
show the values of signals A and B as
hexadecimal numbers.
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