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Enter the decimal equivalent to output "res" value in the following Verilog code after three rising edge of the clock with dir = 1, followed by two rising edge of the clock with dir = 0. module TesQ (clk, dir, res); input wire clk, dir; output reg [7:0] res ; integer i;   initial begin  res = 8'b10000;  end   always @ (posedge clk) begin             if (dir) begin res = res + 8'b101;  end            else begin res = res - 8'b11;  end    end endmodule

Enter the decimal equivalent to output "res" value in the following Verilog code after three rising edge of the clock with dir = 1, followed by two rising edge of the clock with dir = 0. module TesQ (clk, dir, res); input wire clk, dir; output reg [7:0] res ; integer i;   initial begin  res = 8'b10000;  end   always @ (posedge clk) begin             if (dir) begin res = res + 8'b101;  end            else begin res = res - 8'b11;  end    end endmodule

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Enter the decimal equivalent to output "res" value in the following Verilog code after three rising edge of the clock with dir = 1, followed by two rising edge of the clock with dir = 0.

module TesQ (clk, dir, res);
input wire clk, dir;
output reg [7:0] res ;
integer i;
  initial begin  res = 8'b10000;  end
  always @ (posedge clk) begin
            if (dir) begin res = res + 8'b101;  end
           else begin res = res - 8'b11;  end
   end
endmodule

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