For simplicity, let us assume that each instruction on a RISC processor is executed in 2 microseconds and that an I/O device can only wait for an interrupt to be handled for a maximum of 1 millisecond before it is serviced. The number of instructions that may be executed when interruptions are deactivated is restricted to a certain number.

For simplicity, let us assume that each instruction on a RISC processor is executed in 2 microseconds and that an I/O device can only wait for an interrupt to be handled for a maximum of 1 millisecond before it is serviced. The number of instructions that may be executed when interruptions are deactivated is restricted to a certain number.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
For simplicity, let us assume that each instruction on a RISC processor is executed in 2 microseconds and that an I/O device can only wait for an interrupt to be handled for a maximum of 1 millisecond before it is serviced. Do you know how many instructions may be executed with interrupts deactivated before they reach a specific number of instructions?
Let us suppose, for the sake of simplicity, that each instruction on a RISC processor is processed in 2 microseconds and that an I/O device can only wait for an interrupt to be handled for a maximum of 1 millisecond before it is serviced. When interruptions are turned off, the number of instructions that may be performed is limited.
So let's say that each instruction is executed in about two microseconds by a RISC processor. An I/O device can only wait for about 1 millisecond before its interrupt is handled. When interrupts are turned off, how many instructions can be run?
Assume an I/O device may only wait for an interrupt to be handled for up to 1 millisecond, and that a RISC processor executes each instruction in 2 microseconds. There is a hard limit on the number of instructions that may be executed with interruptions deactivated.
Assume that a RISC processor executes each instruction in 2 microseconds and that an I/O device can wait no more than 1 millisecond for an interrupt to be handled. There is a limit on the number of instructions that may be executed with interrupts deactivated.
Assume that a RISC processor executes each instruction in 2 microseconds and that an I/O device can only wait for 1 millisecond before its interrupt is handled. What is the maximum number of instructions that may be performed when interruptions are disabled?
Assume that a RISC processor executes each instruction in 2 microseconds and that a 1/O device can only wait for an interrupt to be serviced for 1 millisecond before it is serviced. The number of instructions that may be executed when interruptions are deactivated is restricted.
Assume that a RISC processor executes each instruction in two microseconds and that an I/O device can wait no more than one millisecond before its interrupt is handled. How many instructions can be performed with interruptions disabled?
A RISC instruction pipeline has five stages with propagation delays of 20 ns, 25 ns, 20ns, 70 ns, and 40 ns, respectively. What is the clock period? If a non-pipelined CPU can process an instruction in 160 ns, what is the actual steady-state speedup of the pipeline?
Briefly explain the two basic approaches used to minimize register-memoryoperations on RISC machines.
Consider a CPU that operates with a data transfer rate of 30 Mbytes/s. The data is transferred byte-wise and the CPU has to transfer 30bytes of data, and the size of the Status register is 4 bytes. What is the total time needed to perform the data transfer?