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For the given program segment, the performance of implementation on FPGA board is not as per the expectation, suggest possible options to rectify the mistakes.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity E1 is port ( A,B: in bit; X: out bit ); end E1; architecture E11 of E1 is begin process(A) begin if A=’0’ then X<=’1’; elsif B=’1’ then X<=’0’; else X<=’0’; end if; end process; end E11;

For the given program segment, the performance of implementation on FPGA board is not as per the expectation, suggest possible options to rectify the mistakes.  library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity E1 is port ( A,B: in bit; X: out bit ); end E1; architecture E11 of E1 is begin process(A) begin if A=’0’ then X<=’1’; elsif B=’1’ then X<=’0’; else X<=’0’; end if; end process; end E11;

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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For the given program segment, the performance of implementation on FPGA board is not
as per the expectation, suggest possible options to rectify the mistakes. 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity E1 is port ( A,B: in bit; X: out bit );
end E1;
architecture E11 of E1 is
begin
process(A)
begin
if A=’0’ then X<=’1’;
elsif B=’1’ then X<=’0’;
else X<=’0’;
end if;
end process;
end E11;

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