Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
Given the following cache and cache configuration: 2-way set associative 4 byte cache line 32 byte cache 10 bit address Assume a write-back cache TAG SET OFFSET 6 2 2 Assume that the cache will replace data in block 0 before lines in block 1 when replacement is required for this question. Data (3..0) A5 06 72 B4 Block# Tag (binary) 010110 010010 Valid Dirty Set Index = 0 1 A5 06 72 B4 010110 3A 59 BC 94 ЗА 59 ВС 94 Set Index = 1 1 1 010111 1 1 Set Index = 2 111111 FF FF FF FF 1 1 110011 19 FD E4 FF 1 1 100100 000011 A4 4A 56 65 A4 4A 56 65 1 1 Set Index = 3 1 For each of the following memory operations fill in the blocks given with the result of the operation on the cache. Use MM to indicate unknown data fetched from memory. The entry below is completed for you as an example of what to do. Operation: CPU reads from $360 Hit(H) or Miss(M): M Fetch from memory? _ No X Yes, from $360 to $363 Valid Dirty Data (3..0) MM MM MM MM --Result-- Block# Tag (binary) 110110 Set Index = 0 1 Operation: CPU writes $FF to $24E Hit(H) or Miss(M): Fetch from memory? _ No _ Yes, from to --Result-- Block# Tag (binary) Data (3..0) Valid Dirty Set Index =

Given the following cache and cache configuration: 2-way set associative 4 byte cache line 32 byte cache 10 bit address Assume a write-back cache TAG SET OFFSET 6 2 2 Assume that the cache will replace data in block 0 before lines in block 1 when replacement is required for this question. Data (3..0) A5 06 72 B4 Block# Tag (binary) 010110 010010 Valid Dirty Set Index = 0 1 A5 06 72 B4 010110 3A 59 BC 94 ЗА 59 ВС 94 Set Index = 1 1 1 010111 1 1 Set Index = 2 111111 FF FF FF FF 1 1 110011 19 FD E4 FF 1 1 100100 000011 A4 4A 56 65 A4 4A 56 65 1 1 Set Index = 3 1 For each of the following memory operations fill in the blocks given with the result of the operation on the cache. Use MM to indicate unknown data fetched from memory. The entry below is completed for you as an example of what to do. Operation: CPU reads from $360 Hit(H) or Miss(M): M Fetch from memory? _ No X Yes, from $360 to $363 Valid Dirty Data (3..0) MM MM MM MM --Result-- Block# Tag (binary) 110110 Set Index = 0 1 Operation: CPU writes $FF to $24E Hit(H) or Miss(M): Fetch from memory? _ No _ Yes, from to --Result-- Block# Tag (binary) Data (3..0) Valid Dirty Set Index =

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question
table
Given the following cache and cache configuration: 2-way set associative 4 byte cache line 32 byte cache 10 bit address Assume a write-back cache TAG SET OFFSET 2 Assume that the cache will replace data in block 0 before lines in block 1 when replacement is required for this question. Data (3..0) A5 06 72 B4 A5 06 72 B4 Block# Tag (binary) 010110 Valid Dirty Set Index = 0 1 010010 Set Index = 1 010110 010111 3A 59 BC 94 1 1 3A 59 BC 94 1 1 111111 110011 Set Index = 2 FF FF FF FF 19 FD E4 FF 1 1 1 1 1 Set Index = 3 1 100100 000011 A4 4A 56 65 1 A4 4A 56 65 For each of the following memory operations fill in the blocks given with the result of the operation on the cache. Use MM to indicate unknown data fetched from memory. The entry below is completed for you as an example of what to do. Operation: CPU reads from $360 Hit(H) or Miss(M): M Fetch from memory? No X Yes, from $360 to $363 Valid Dirty Tag (binary) 110110 --Result-- Block# Data (3..0) Set Index = 0 MM MM MM MM 1 Operation: CPU writes $FF to $24E Hit(H) or Miss(M): Fetch from memory? No _ Yes, from to --Result-- Block# Tag (binary) Data (3..0) Valid Dirty Set Index =
Transcribed Image Text:Given the following cache and cache configuration: 2-way set associative 4 byte cache line 32 byte cache 10 bit address Assume a write-back cache TAG SET OFFSET 2 Assume that the cache will replace data in block 0 before lines in block 1 when replacement is required for this question. Data (3..0) A5 06 72 B4 A5 06 72 B4 Block# Tag (binary) 010110 Valid Dirty Set Index = 0 1 010010 Set Index = 1 010110 010111 3A 59 BC 94 1 1 3A 59 BC 94 1 1 111111 110011 Set Index = 2 FF FF FF FF 19 FD E4 FF 1 1 1 1 1 Set Index = 3 1 100100 000011 A4 4A 56 65 1 A4 4A 56 65 For each of the following memory operations fill in the blocks given with the result of the operation on the cache. Use MM to indicate unknown data fetched from memory. The entry below is completed for you as an example of what to do. Operation: CPU reads from $360 Hit(H) or Miss(M): M Fetch from memory? No X Yes, from $360 to $363 Valid Dirty Tag (binary) 110110 --Result-- Block# Data (3..0) Set Index = 0 MM MM MM MM 1 Operation: CPU writes $FF to $24E Hit(H) or Miss(M): Fetch from memory? No _ Yes, from to --Result-- Block# Tag (binary) Data (3..0) Valid Dirty Set Index =
Expert Solution
steps

Step by step

Solved in 2 steps with 1 images

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS