goal is to calculate this equation in MIPS: v0 = 4*a2 + (3*a1 - a0) Just the register value, nothing to print.
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Computer Science
The goal is to calculate this equation in MIPS:
v0 = 4*a2 + (3*a1 - a0)
Just the register value, nothing to print.
Step by step
Solved in 2 steps
- Suppose the register %rax contains 0x100, and the register %rbx contains 0x10. What value is stored in %rcx as a result of movq 2(%rax,%rbx,4), %rcx?1. Design a 4-bit ALU that performs Arithmetic (add, subtraction), and Logicoperations (AND, OR). The following control signals are to be considered:• A/S: add/subtract (0:add, 1:subtract)• A/O: and/or (0:and, 1:or)• A/L: arithmetic/Logic (0:arithmetic, 1:logic)• R/W: read/write signal (0:read, 1:write) Unit 3 (A/L) - Design a 4-bit ALU using Unit 1 and Unit 2. The control signal A/L willindicate which operation the ALU will perform (when the control signal is 0 performArithmetic, otherwise if the signal is 1 then perform Logic).Unit 4 (R/W)- Design three 4-bit parallel registers to hold A, B, and C where C keepsthe output of the ALU. The registers have a R/W control signal that indicates that theyare being written to or read from.This is a seven segment display. can you implement this on multisim and and show the letters M A H D I J A N on the display using jk flip flops. we need 555 timer counter. frequency should be 1hz.
- Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: an asynchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: an asynchronous Active Low Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active Low Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.1. Design a 4-bit ALU that performs Arithmetic (add, subtraction), and Logicoperations (AND, OR). The following control signals are to be considered:• A/S: add/subtract (0:add, 1:subtract)• A/O: and/or (0:and, 1:or)• A/L: arithmetic/Logic (0:arithmetic, 1:logic)• R/W: read/write signal (0:read, 1:write) The details of each control signal (Unit) are as follows.Unit 1 (A/S) - Design a 4-bit adder/subtractor that accepts two 4-bits numbers, A andB, and either add them up (A + B) or subtract them (A – B) depending on a controlsignal A/S (when the control signal is 0 perform ADD, otherwise if the signal is 1 thenperform SUB). The result will be stored in C.Unit 2 (A/O) - Design a 4-bit AND/OR unit that accepts two 4-bits numbers, A and B,and either AND them or OR them depending on a control signal A/O (when the controlsignal is 0 perform AND, otherwise if the signal is 1 then perform OR – bitwise logicaloperation). The result will be stored in C.Unit 3 (A/L) - Design a 4-bit ALU using Unit…
- The code is in RISC V For this part write the binary code/machine level code of the following instructions (all offsets in decimal numbers): ld x5, 6(x2) xor x6, x5, x1 sh x6, -3(x2) ble x9, x13, -348Please answer the following question using only one 3-bit binary counter with clear input and the minimum number of components listed below, design a counter that generates the following sequence repeatedly: 0-> 3 -> 5 -> 7 -> 9 -> 11-> 13 -> 0 -> 3 -> 5 -> 7 …… Information: E is enable input. When E = 1, it counts at every clock cycle. When E = 0, it stops counting and output stays unchanged. clr is clear input. When clr = 1, it starts counting from 0 from the next clock cycle if E = 1. The only allowed components are: a) 3-bit binary counter b) left and right shifter c) Logic Gates (And, Or, Not) PLEASE USE THE 3-BIT COUNTER DESIGN BELOW WHEN DESIGNING THE COUNTERComputer Science Write an ALP to implement the equation (N12-N22)/N3 assume N1, N2 and N3 are 8 bit numbers and store the quotient in the DL register and Remainder in the CL register.
- Please answer the following question using only one 3-bit binary counter with clear input and the minimum number of components listed below, design a counter that generates the following sequence repeatedly: 0-> 3 -> 5 -> 7 -> 9 -> 11-> 13 -> 0 -> 3 -> 5 -> 7 …… Note: E is enable input. When E = 1, it counts at every clock cycle. When E = 0, it stops counting and output stays unchanged. clr is clear input. When clr = 1, it starts counting from 0 from the next clock cycle if E = 1. The allowed components are: a) 3-bit binary counter b) left and right shifter c) Logic Gates (And, Or, Not) (the number of input pins are not limited, which means that you can have more than 2 input pins)Write an ALP to implement the equation (N12-N22)/N3 assume N1, N2 andN3 are 8 bit numbers and store the quotient in the DL register andRemainder in the CL register.1. Design a SINGLE 4-bit ALU that performs Arithmetic (add, subtraction), and Logicoperations (AND, OR). The following control signals are to be considered:• A/S: add/subtract (0:add, 1:subtract)• A/O: and/or (0:and, 1:or)• A/L: arithmetic/Logic (0:arithmetic, 1:logic)• R/W: read/write signal (0:read, 1:write) The details of each control signal (Unit) are as follows. Unit 1 (A/S) - Design a 4-bit adder/subtractor that accepts two 4-bits numbers, A andB, and either add them up (A + B) or subtract them (A – B) depending on a controlsignal A/S (when the control signal is 0 perform ADD, otherwise if the signal is 1 thenperform SUB). The result will be stored in C. Unit 2 (A/O) - Design a 4-bit AND/OR unit that accepts two 4-bits numbers, A and B,and either AND them or OR them depending on a control signal A/O (when the controlsignal is 0 perform AND, otherwise if the signal is 1 then perform OR – bitwise logicaloperation). The result will be stored in C. Unit 3 (A/L) - Design a 4-bit ALU…