How should the processor handle a cache request when writing a block from the write buffer to main memory?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?How should the processor handle a cache request when writing a block from the write buffer to main memory?If a cache request comes in while a block is being written back into main memory from the write buffer, what should the processor do?
- What should the processor do if a cache request can't be completed while a block is being written back into main memory from the write buffer?What should the processor do if a cache request cannot be satisfied while a block is being written from the write buffer back into main memory?If the processor cannot fulfill a cache request when writing a block from the write buffer to main memory, what should it do?
- What should the processor do if a cache request arrives while a block is being flushed back into main memory from the write buffer?What should the CPU do if a cache request arrives while a block is being returned from the write buffer to main memory?If the processor requests a cache hit while flushing a block from the write buffer to main memory, what should happen?