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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?A two way set associative cache can host 32 KB (Kilobyte) of memory data with 16-word block. The memory system has 32 bits address bus. How many total bits does this cache have. (include 1 validation bit for each cache line, assume each word is one byte long).
- A computer has a 256 KB, K-way set associative write-back data cache with block size of 32 B. The address sent to the cache controller by the processor is of 32 bits. In addition to the address tag, each cache tag directory contains 2 valid bits and 1 modified bit. If 16 bits are used to address tag. What is the minimum value of K?A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressing is used.Q.) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.The hit rate of the memory closest to the ALU is increased from 75% to 80% in a practical cache memory hierarchy. The hit latency (or hit time) for the closest memory is 20ps, while the miss latency is 20ns. What would the expected reduction in the average memory access latency be?
- A cache memory system with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 14 bits. If it is designed as a 4-way set associative cache, the length of the TAG field will be ………… bits.Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
- Ifthere is a 64K cache with a block size of 7k, what is the number of bits in the indes field of block address, given the cache is (3) F Associative, (b) Direct Mapped, (¢) 2-way Sct Associative, and ) 4 - way Set Associative. bA certain computer system is consisting of 32 GB main memory and 32 MB cachememory. The cache uses 8 bytes word.a. Using cache direct mapping, determine the size of the tag, line and word.b. Using cache associative mapping, show the main memory address format.c. The computer uses a 2-way set associative mapping cache structure. Show the mainmemory address format.Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
