2. In a kway set associative cache, the cachedivided inkov se, cach of which cormists ofk lines The lines of a set are placed insequence cne afler another. The lings isare sequenced before the hines in set (stnThe main memory blocks are sunbered oonwands. The main memery block mnberedmust be mapped to anry one of the cache linesfrom

Number of sets in cache = v. So, main memory block j will be mapped to set (j mod v), which will be…

Ina kwy set asociative cache, the cache livided inte v s, of which comists o lines The lines of a set we placed sequence one afler another The lines is aet are sequenced before the ines in set (sti The main memory blocks are sunted ands. The main memey block nanbered ust be mapped to any one of the cache lines w rom

Ina kwy set asociative cache, the cache livided inte v s, of which comists o lines The lines of a set we placed sequence one afler another The lines is aet are sequenced before the ines in set (sti The main memory blocks are sunted ands. The main memey block nanbered ust be mapped to any one of the cache lines w rom

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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a) Execute the above program by setting block size = 4 and cache size = 8, 16 and 32.Record the observation in the following table for various values of “num” in theprogram.LRU Replacement Algorithmnum Block Size Cache size # Hits # Misses %Hit Ratio4 84 16104 324 84 16154 324 84 16204 324 84 16254 32b) Comment on the result obtained in the above table by keeping in mind the locality ofreference.c) Compare the performance of Associative mapped cache and Direct Mapped Cache
Assume there are three small caches, each consisting of four one word blocks. One cache isfully associative, a second is two way set associative, and the third is direct mapped. Find thenumber of misses for each cache organization given the following sequence of block addresses:1,7, 6, 5, 1, and 7.
“Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when a particular cache block is accessed. One example of prefetching is a stream buff er that prefetches sequentially adjacent cache blocks into a separate buff er when a particular cache block is brought in. If the data is found in the prefetch buff er, it is considered as a hit and moved into the cache and the next cache block is prefetched. Assume a two-entry stream buff er and assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. What is the miss rate for the address stream above?Cache block size (B) can aff ect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes. 8: 4% 16: 3% 32: 2% 64: 1.5% 128: 1%…
CA_7 Let a program use 5 contiguous words and loop these words 100 times (meaning the execution trace of this program is [012340123401234...1. Furthermore, let a cache have 4 word-sized blocks. How many misses will there be if the cache is: (a)Direct mapped? (b) Fully-associative with commonly used Least-Recently-Used replacement? (c) Fully-associative with less well-known Most-Recently-Used replacement? (d) Set-associative with two sets and uses first-in-first-out replacement? (e) Set-associative with two sets and uses first-in-last-out replacement?
Suppose the head of a moving head disk with 200 tracks numbered 0-199 is currently servinga request at track 143. It has just finished a request at track 125. If the queue of requests iskept in the FIFO order,86,147,85,177,94,150,102,175,130What is the total head movement to satisfy these requests for the following disk schedulingalgorithms? First Come First Served Shortest Seek Time First SCAN
Develop a C/C++ program that accepts the name of a memory trace file as a command line argument. Use the data to simulate a set associative cache using LRU replacement. Additional command line arguments will be needed to identify the details of the simulated cache. The arguments should appear in the following order: the memory trace input file X, where 2X == the number of direct-mapped sets Y, where 2Y == the number of blocks per set Z, where 2Z == the number of cached words per block Your program (say it's a compiled C program) could be run like this: ./cache data.tra 3 2 4 This would simulate an 8 set associative LRU cache with 4 blocks per set, where each block caches 16 addresses. NOTE… the reason I've chosen to use exponents for arguments is to ensure we have powers of 2 for everything. Trace File The trace file is line based with each line containing a memory address requested, in hex. Please note this data is real, so the addresses are larger than 32-bits. In…
Make the difference between a cache that is directly mapped and one that is totally associative.
Write a C program that implements FIFO and LRU page-replacement algorithms. The code should take in only one command line argument, which will be the filename of the input file which contains a page-reference sequence. The output of the program should print the same information as the images attached. NOTE: the resulting cache state is kept in their respective orders.
Suppose that immediately following the two read operations of question 1,the program does read operations on the following memory addresses (e.g., with “lb”or “lw” instructions): 148, 224, 556, 248 (again), 6728, 1312 (again), and 128.Assuming the cache was empty prior to the read operations of question 1, state whichof these read operations will result in cache hits, assuming a 2-way set-associativecache with a total capacity of 4 eight-word blocks and LRU replacement in each set. Suppose that a program does read operations on the following memory addresses (e.g., with “lb” or “lw” instructions): 248, 1312. Give the number of the memory block that each of these addresses belongs to, for each of the following memory block sizes. A. block size of one word (4 bytes) B. block size of eight words (32 bytes) just do the first part
Draw a line between a cache that is fully associative and one that is directly mapped out.
For a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
Assume a direct-mapped cache that holds 4096 bytes, in which each block is 16 bytes. Assuming that an address is 32 bits and that cache is initially empty, complete the table that follows.(You should use hexadecimal numbers for all answers.) Which, if any, of the addresses will cause a collision (forcing the block that was just brought in to be overwritten) if they are accessed one right after the other?