OEL There is a 256 byte, 4-way set associative cache where each cache block contains 16 bytes on a processor with 216 are zero). Suppose we are accessing the memory addresses in the order of: addressable bytes of memory. Assume that the cache is initially empty (all valid bits Ox0010, Ox0032, 0×03B8, 0x0035, 0x0027, Ox00AF. a) How many of these address requests are hits/misses? b) What is the hit ratio? c) How many blocks are replaced?

Computer Networking: A Top-Down Approach (7th Edition)
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O5L There is a 256 byte, 4-way set associative cache where each cache block contains 16 bytes on a 16-bit
processor with 2*º addressable bytes of memory. Assume that the cache is initially empty (all valid bits
are zero). Suppose we are accessing the memory addresses in the order of:
Ox0010, Ox0032, 0×03B8, 0x0035, 0x0027, 0×00AF.
a) How many of these address requests are hits/misses?
b) What is the hit ratio?
c) How many blocks are replaced?
Transcribed Image Text:O5L There is a 256 byte, 4-way set associative cache where each cache block contains 16 bytes on a 16-bit processor with 2*º addressable bytes of memory. Assume that the cache is initially empty (all valid bits are zero). Suppose we are accessing the memory addresses in the order of: Ox0010, Ox0032, 0×03B8, 0x0035, 0x0027, 0×00AF. a) How many of these address requests are hits/misses? b) What is the hit ratio? c) How many blocks are replaced?
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