onsider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. (I have been deliberately vague about some of the details here, as I want you to think about what makes sense in terms of when the branch outcome is known and branch target computed.) SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)
onsider a fairly standard 5-stage pipeline: Fetch; Decode; Execute; Memory; Writeback. Let the processor be a nice, simple RISC single-cycle machine. The instructions below are executed. The branch should be taken — however, this processor does no prediction and always assumes a fall-through. Draw a Gantt chart for this and determine the branch penalty. (I have been deliberately vague about some of the details here, as I want you to think about what makes sense in terms of when the branch outcome is known and branch target computed.) SUB R1, R1, #1 BEQ R1, R0, LoopDone LOAD R2, Memory(100) SUB R3, R2, R1 MUL R3, R3, R3 LOAD R4, Memory(200) ADD R5, R4, R3 STORE R5, Memory(204)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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onsider a fairly standard 5-stage pipeline: Fetch; Decode; Execute;
Memory; Writeback. Let the processor be a nice, simple RISC single-cycle
machine. The instructions below are executed. The branch should be
taken — however, this processor does no prediction and always assumes
a fall-through.
Draw a Gantt chart for this and determine the branch
penalty. (I have been deliberately vague about some of the details here,
as I want you to think about what makes sense in terms of when the
branch outcome is known and branch target computed.)
SUB R1, R1, #1
BEQ R1, R0, LoopDone
LOAD R2, Memory(100)
SUB R3, R2, R1
MUL R3, R3, R3
LOAD R4, Memory(200)
ADD R5, R4, R3
STORE R5, Memory(204)
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