Q7. A processor has a clock frequency of 1GHZ, we run a program consisting 10 billion instructions on this processor. The program has the following instruction mix. (07.1 & Q7.2 use same information Instruction class ALU Branch Jump Load Store % of program 50% 30% 10% 5% 5% Q7.2 The execution times in seconds is a) 3.65 b) 3.55 c) 35.5 d) Non of the above CPI 4 3 2 5

Q7. A processor has a clock frequency of 1GHZ, we run a program consisting 10 billion instructions on this processor. The program has the following instruction mix. (07.1 & Q7.2 use same information Instruction class ALU Branch Jump Load Store % of program 50% 30% 10% 5% 5% Q7.2 The execution times in seconds is a) 3.65 b) 3.55 c) 35.5 d) Non of the above CPI 4 3 2 5

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.
Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
Assume (hypothetically) that there is a version of QtSpim that simulates a 4-core processor. Write a MIPS Assembly program that would take advantage of the 4 cores to speed up the execution of mathematical calculations. Specifically, write a program that receives as input two arrays of equal length, and replaces the content of each element in Array 1 with the sum of the corresponding elements in Array 1 and 2.
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
Consider a program that declares global integer variables x, y[10]. Thesevariables are allocated starting at a base address of decimal 1000. All thesevariables have been initialized to zero. The base address 1000 has been placed in$gp. The program executes the following assembly instructions:lw $s1, 0($gp)addi $s1, $s1, 25sw $s1, 0($gp)lw $s2, 12($gp)add $s2, $s2, $s1sw $s2, 8($gp)sw $s2, 12($gp) What are the memory addresses of variables x, y[0], and y[1]? What are the values of variables x, y[0], y[1], and y[2] at the endof the program?
Assume a program has 20% store and load. When we run this program in a computer, we observe that L1 instruction cache has a hit rate of 98% and L1 data cache has a hit rate of 96%. The L2 cache has a hit rate of 80%. The access time of L1 cache is 2 cycle, and the access time of L2 cache is 40 cycles. If a miss occurs in L2, we have to go to main memory and the penalty is 100 cycles. Assume that the cache uses physical address.a) Without a TLB, what is the AMAT?b) Assume a TLB is built in the cache and its access time is ignored. If the TLB has a 99% hit rate, what is the new AMAT?c) If there is a 0.01% chance that a page fault happens, and the penalty to fetch a page from the disk is 106cycles, what is the new AMAT?
A CPU has an instruction pipeline with the following 4 segments. 1.F1(Fetch Instruction) 2.DA(Decode, Address) 3.FO(Fetch Operand) 4.EX(Execution) D1: Add R1,R2 //R1=R1+R2 Add R4,R1 //R4=R4+R1 Add R4,R3 //R4=R4+R3 Cmp R4,R5 // compare R4 and R5 Jg D1 //if Jump Greater (if R4>R5) Sub R2,R1 //R2=R2-R1 Sub R2,R3 //R2=R2-R3 Jmp D1
Q1: Suppose the hypothetical processor has two I/O instructions: (3+3+3)0011=Load AC from I/O0111=Store AC to I/OIn this case, the 12-bit address identifies a particular external device. Show the program execution using figure for the following program:a) Load AC from device 6b) Add contents of memory location 880c) Store AC to device 7 (Note: Question is to be solved similar to the pictures attached with minimum explaination of a line or two with the steps and SHOULD include the memory location 880 as stated in the question)
Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?
1. T/F - if (B)=006000 (PC)=003600 (X)=000090, for the machine instruction 0x032026, the target address is 003000.2. T/F – PC register stores the return address for subroutine jump.3. T/F – S register contains a variety of information such as condition code.4. T/F – INPUT WORD 1034 – This means Operating system should reserve 1034 bytes in memory5. T/F - In a two pass assembler, adding literals to literal table and address resolution of local symbol are done using first pass and second pass respectively.
We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?