Question 1: Encoding branches & immediates We want to design a new K-format instruction for a branch-equal-immediate. A: What information would need to be encoded in a beq R2, 7, loop instruction? B: Why can't we have a beq R2, 7, loop instruction? and C: How could we fix this? Hint: think about the instruction encodings and what we need to encode such an instruction. Name Bit Fields A: beq R2, 7, loop needs to encode: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-Format op rs rt rd shmt funct I-format op rs rt address/immediate (16) J-format op target address (26) B: Why can't we have this with the R/I/J formats? K-format C: What tradeoff could we make to implement a K-format?

Question 1: Encoding branches & immediates We want to design a new K-format instruction for a branch-equal-immediate. A: What information would need to be encoded in a beq R2, 7, loop instruction? B: Why can't we have a beq R2, 7, loop instruction? and C: How could we fix this? Hint: think about the instruction encodings and what we need to encode such an instruction. Name Bit Fields A: beq R2, 7, loop needs to encode: 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-Format op rs rt rd shmt funct I-format op rs rt address/immediate (16) J-format op target address (26) B: Why can't we have this with the R/I/J formats? K-format C: What tradeoff could we make to implement a K-format?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
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