Question 1 Listen Cache memory is faster than the registers. True False Question 2 Listen The following subtraction of two Hexadecimal number is correct. 8B02-7A02 = 1100 True False
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- QUESTION 7 Choose the correct instruction that will read data in from an I/O device. IN AL, 60 IN 60, AL OUT 60, AL OUT AL, 60 MOV AL, 60 MOV 60, AL QUESTION 8 The mask _____ can be used to isolate bit #2 of an 8-bit register. 00 H FF H 02 H 04 H QUESTION 10 Motorola processors use ___________, unlike Intel processors. a Memory-mapped I/O b Interrupts c Peripheral I/O d ParityFor the 8051 family of microcontrollers:i) Draw a representative memory map and explain how part of the data memory isable to share the same address space as the Special Function Registers in thecase of the 8052. ii) When an 8051 device is switched on, which memory bank is active? Explain howyou can switch to memory bank 1? iii) Explain why you should be very careful if you use a memory bank other thanmemory bank 0 if also using push and pop instructions. How can this issue beavoided?To the best of your ability, calculate the minimal number of bits required in the MAR for each of the following memory sizes. What is the real number of memory cells in a 640 KB memory unit that is claimed to have 640 KB? What do you think about 512 MB of RAM? What do you think about 2 GB of RAM? Explain the role that read-only memory (ROM) plays in the architecture of a computer system and why it is used. What kind of information is stored in read-only memory (ROM), and how does that information get into the memory in the first place?
- Explain the following code segments including lui $t0, 0xffff Wait: lw $t1, 0($t0) andi $t1, $t1, 0x0001 beq $t1, $zero, Wait lw $v0, 4($t0) What kind of registers we should use? What is the name of the registers? What do we call these code sequences in MIPS? Explain the memory layout where the registers are located Why do we need to loop? For what should we wait? When the 'ready' bit is changed? The purpose of and instruction The actual meaning of "lw $v0, 4($t0)" Explain the following code segments including lui $t0, 0xffff Wait: lw $t1, 0($t0) andi $t1, $t1, 0x0001 beq $t1, $zero, Wait lw $v0, 4($t0) What kind of registers we should use? What is the name of the registers? What do we call these code sequences in MIPS? Explain the memory layout where the registers are located Why do we need to loop? For what should we wait? When the 'ready' bit is changed? The purpose of and instruction The actual meaning of "lw $v0, 4($t0)"Aim: - Write program to add 3 hexadecimal numbers stored in the memory location (not in registers).Before adding the second number should be incremented once and the third number should be incremented twice. The result of the addition must be stored in another memory location. Platform Required:- sim8085.comCS 218: Assembly Language and Systems Programming Given the following code fragment: mov rax, 4 mov rbx, 3 imul rbx What would be in the below 64-bit registers after execution (in hex)? rax rdx Must answer in hex (must precede number with 0x).
- (a) How many 32 K×8 RAM chips are needed to provide a memory capacity of 256 K bytes?1. How many lines of the address must be used to access 256 K bytes? How many of these lines are connected to the address inputs of all chips?2. How many lines must be decoded for the chip select inputs? Specify the size of the decoder.2. This question is about Digital Logic and Address DecodingA computer is being designed using a microprocessor with a 16-bit address bus (A0—A15, where A0 is the least significant bit). The 64K address space is to be split betweenand allocated to RAM, ROM and I/O hardware as follows:Address Range (hex) Contains Select Signal0x0000 — 0x1FFF Main RAM RAMCS0x8000 — 0x9FFF Video RAM VRAMCS0xB000 — 0xBFFF I/O hardware IOCS0xC000 — 0xCFFF BASIC ROM BROMCS0xF000 — 0xFFFF OS ROM OSROMCSThe rest of the address space is unused.Note: As with many computer systems, it its only necessary to decode addresses to sufficiently identify each of the sections above uniquely. It is acceptable for some parts to be decodeable by more than one address provided these extra addresses do not overlap any of the other specified address ranges. Using a combination of AND, OR and NOT gates and the signals (A12 — A15) that contain the top four bits of the address in binary form: a. Derive the equation for a logic…q) How the operation of software interrupt instructions differs i.e. INT, INTO, INT 3, and BOUND? q) Dynamic RAM (DRAM) retains data for only a short period (usually 2–4 ms) creatingproblems for the memory system designer. What type of mechanism is required to overcome this problem in DRAMs? q) What are the three common methods of expanding the interrupt structure of themicroprocessor? Explain any one of them along with example.
- . set Explain the reason for the number of bits being used for Tag and for the number of bits required for RAM address? for 4way , fully (simple ansewer for each one )Topic: Computer Science, CPU Architecture and Assembly Programming 1. Write ASL programs in EMU8086 to accomplish the following tasks. a) Evaluate (5 + 4) * 36. Your solution should store the answer in the Ax register. b). Evaluate (420 + 312) *300 and explain where is the result of the multiplication. You need to use 2 bytes registers like Ax, Bx, Cx, Dx… to store these type of data that are greater than 255.Which of the following is true? 1) the 80/20 rule states that 80% of the instructions is excutede and 20% of the instruction is generated. 2) in von Neumann architecture, external bus is for data memory only