SOLVE IT AS NEW DONT SPAM SOLUTION FROM ANOTHER QUESTIONS TY. Using a table similar to that shown in Figure 3.10, calculate 35 divided by 11 using the hardware described in Figure 3.8. You should show the contents of each register on each step. Assume both inputs are unsigned 6-bit integers.

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SOLVE IT AS NEW DONT SPAM SOLUTION FROM ANOTHER QUESTIONS TY.

Using a table similar to that shown in Figure 3.10, calculate 35 divided by 11
using the hardware described in Figure 3.8. You should show the contents of
each register on each step. Assume both inputs are unsigned 6-bit integers. 

Iteration
Step
Quotient
Divisor
Remainder
0000 0111
0110 0111
Initial values
0000
0010 0000
1: Rem = Rem - Div
0000
0010 0000
2b: Rem < 0= +Div, sll Q. Q0 = 0
3: Shift Div right
1
0000
0010 0000
0000 0111
0000
0001 0000
0000 0111
1: Rem = Rem – Div
0000
0001 0000
0111 0111
2b: Rem <0= +Div, sll Q. Q0 = 0
3: Shift Div right
2
0000
0001 0000
0000 0111
0000 0111
0111 1111
0000
0000 1000
1: Rem = Rem - Div
0000
0000 1000
2b: Rem <0 +Div, sll Q. Q0 = 0
3: Shift Div right
3
0000
0000 1000
0000 0111
0000
0000 0100
0000 0111
1: Rem = Rem - Div
0000
0000 0100
@o00 0011
2a: Rem 20= sll Q. Q0 =1
3: Shift Div right
4
0001
0000 0100
0000 0011
0001
0000 0010
0000 0011
1: Rem = Rem – Div
0001
0000 0010
Co00 0001.
2a: Rem 20= sll Q. Q0 = 1
0011
0000 0010
0000 0001
3: Shift Div right
0011
0000 0001
0000 0001
FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determine
Transcribed Image Text:Iteration Step Quotient Divisor Remainder 0000 0111 0110 0111 Initial values 0000 0010 0000 1: Rem = Rem - Div 0000 0010 0000 2b: Rem < 0= +Div, sll Q. Q0 = 0 3: Shift Div right 1 0000 0010 0000 0000 0111 0000 0001 0000 0000 0111 1: Rem = Rem – Div 0000 0001 0000 0111 0111 2b: Rem <0= +Div, sll Q. Q0 = 0 3: Shift Div right 2 0000 0001 0000 0000 0111 0000 0111 0111 1111 0000 0000 1000 1: Rem = Rem - Div 0000 0000 1000 2b: Rem <0 +Div, sll Q. Q0 = 0 3: Shift Div right 3 0000 0000 1000 0000 0111 0000 0000 0100 0000 0111 1: Rem = Rem - Div 0000 0000 0100 @o00 0011 2a: Rem 20= sll Q. Q0 =1 3: Shift Div right 4 0001 0000 0100 0000 0011 0001 0000 0010 0000 0011 1: Rem = Rem – Div 0001 0000 0010 Co00 0001. 2a: Rem 20= sll Q. Q0 = 1 0011 0000 0010 0000 0001 3: Shift Div right 0011 0000 0001 0000 0001 FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determine
Divisor
Shift right
64 bits
Quotient
Shift left
64-bit ALU
32 bits
Remainder
Control
Write
test
64 bits
FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder
Transcribed Image Text:Divisor Shift right 64 bits Quotient Shift left 64-bit ALU 32 bits Remainder Control Write test 64 bits FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder
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