Suppose the implementation of an instruction set architecture uses two classes of instructions, which arecalled A and B. The total dynamic instruction count is 3 x 10^6. Details for the two classes are given inthe table below:ClassCPI% of instructionsA|240%B2.2|60%Complete the following table. Express all answers in scientific notation and round to two decimalplaces, when needed.ClassInstruction CountNumber of Clock Cyclesх 10^х 10^Ax 10^x 10^B

It is given that: total dynamic instruction count = 3 x 106 Processor's clock rate = 3.2 GHz…

Suppose the implementation of an instruction set architecture uses two classes of instructi called A and B. The total dynamic instruction count is 3 x 10^6. Details for the two classes the table below: Class CPI % of instructions 2 40% В 2.2 60% Complete the following table. Express all answers in scientific notation and round to two d

Suppose the implementation of an instruction set architecture uses two classes of instructi called A and B. The total dynamic instruction count is 3 x 10^6. Details for the two classes the table below: Class CPI % of instructions 2 40% В 2.2 60% Complete the following table. Express all answers in scientific notation and round to two d

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter2: Problem Solving Using C++using

Section2.3: Data Types

Problem 9E: (Practice) Although the total number of bytes varies from computer to computer, memory sizes of...

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Follow this steps. Have to Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.
Please,Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
10. Consider the following code: .386 .model flat, stdcall .stack 4096 ExitProcess PROTO, dwExitCode : DWORD .data aVal SDWORD -6 bVal SWORD 19h cVal DWORD 17h .code mov edx, aVal add edx, edx mov eax, 0FFFFFFFFh mov ax, bVal sub edx, eax Show the content of edx and eax after executing each instruction in Hexadecima
Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?
Consider two different implementations, P1 and P2, of the same instruction setarchitecture. There are four classes of instructions (A, B, C, and D).P1 has a clock rate of 1.5 GHz and CPI for each instruction class is as follows:Class CPI for this classA 1B 2C 3D 4P2 has a clock rate of 2.0 GHz and CPI for each instruction class is as follows:Class CPI for this classA 2B 2C 2D 2a. Given a program with 106 instructions divided into classes as follows: 10% classA, 20% class B, 50% class C and 20% class D, which implementation is faster?
Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.
Consider a generic processor executing the following set of machine instructions. Memory location 34 contains a value 20. What statement best express the final outcome? MOV R1, #0 MOV R2, #34 MOV R3, #1034 ADD R1, (R2) MOV (R3), R1 Select one or more A. memory location 20 contains value 1034 B.memory location 1034 contains value 54 C. memory location 1034 contains value 34 D. memory location 20 contains value 34 E. memory location 1034 contains value 20
Consider a program that declares global integer variables x, y[10]. Thesevariables are allocated starting at a base address of decimal 1000. All thesevariables have been initialized to zero. The base address 1000 has been placed in$gp. The program executes the following assembly instructions:lw $s1, 0($gp)addi $s1, $s1, 25sw $s1, 0($gp)lw $s2, 12($gp)add $s2, $s2, $s1sw $s2, 8($gp)sw $s2, 12($gp) What are the memory addresses of variables x, y[0], and y[1]? What are the values of variables x, y[0], y[1], and y[2] at the endof the program?
We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?
Consider two different implementations of the same instruction set architecture. The instructions can be divided into three classes according to their CPI (class A, B, C). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 30% class A, 30% class B, 40% class C, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.
Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?